本文選題：Flash　切入點(diǎn)：可靠性　出處：《蘇州大學(xué)》2016年碩士論文

【摘要】：Flash是一種廣泛應(yīng)用于SoC上的重要存儲(chǔ)器,在高密度數(shù)據(jù)的存儲(chǔ)和嵌入式系統(tǒng)中的應(yīng)用不斷增加。隨著工藝的進(jìn)步,晶體管特征尺寸降低到了十個(gè)納米的數(shù)量級(jí),隨機(jī)摻雜擾動(dòng)等帶來的工藝偏差、閾值電壓降低帶來的高漏電流等也給Flash設(shè)計(jì)帶來了極大的挑戰(zhàn)。論文以Flash存儲(chǔ)器工作的可靠性為研究重點(diǎn),主要對(duì)Flash存儲(chǔ)器的外圍電路中的靈敏放大器電路、電荷泵電路、字線驅(qū)動(dòng)電路和電平轉(zhuǎn)換電路進(jìn)行了優(yōu)化設(shè)計(jì),提高了外圍電路模塊的可靠性�；跇�(biāo)準(zhǔn)CMOS工藝的8Mbits非易失性存儲(chǔ)器。本文系統(tǒng)平臺(tái)建立在Cadence Virtuoso之上,用Hspice進(jìn)行了電路的功能模塊仿真,而整體電路的仿真用的是Hsim軟件,電路版圖使用Laker進(jìn)行繪制。本論文的主要內(nèi)容和研究對(duì)象是:首先,本文對(duì)存儲(chǔ)單元采用何種溝道的浮柵MOS管進(jìn)行了對(duì)比分析,將P溝道浮柵MOS管和N溝道浮柵MOS管的可靠性做了對(duì)比,得出P溝通存儲(chǔ)單元相對(duì)于N溝道存儲(chǔ)單元在可靠性方面的優(yōu)勢(shì),因此本文最終選擇了P溝道浮柵MOS管作為存儲(chǔ)單元。其次,本文研究了Flash存儲(chǔ)器外圍電路中的靈敏放大器電路、電荷泵電路、字線驅(qū)動(dòng)電路和電平轉(zhuǎn)換電路。對(duì)這幾個(gè)外圍電路的傳統(tǒng)電路進(jìn)行分析,找出各自存在的缺點(diǎn),并據(jù)此設(shè)計(jì)出符合要求的電路,通過Hspice對(duì)設(shè)計(jì)出的電路進(jìn)行仿真分析,所設(shè)計(jì)電路都達(dá)到了設(shè)計(jì)目標(biāo)。另外,本文在最后一章節(jié)中首先簡(jiǎn)要介紹了版圖的設(shè)計(jì)布局、布線規(guī)則,之后對(duì)本課題的IP版圖設(shè)計(jì)進(jìn)行了簡(jiǎn)要介紹。然后對(duì)存儲(chǔ)器進(jìn)行整體仿真并對(duì)編程、讀取和片擦除的仿真波形圖進(jìn)行了重點(diǎn)分析。
[Abstract]:Flash is a kind of important memory widely used in SoC. It is widely used in high density data storage and embedded system. With the development of technology, the characteristic size of transistor has been reduced to ten nanometers. The process deviation caused by random doping disturbance and the high leakage current caused by the decrease of threshold voltage have also brought great challenges to the design of Flash. This paper focuses on the reliability of Flash memory. The sensitive amplifier circuit, charge pump circuit, word line drive circuit and level conversion circuit in the peripheral circuit of Flash memory are optimized. The reliability of the peripheral circuit module is improved. The 8Mbits non-volatile memory based on standard CMOS technology is built on the platform of Cadence Virtuoso. The function module of the circuit is simulated by Hspice, and the whole circuit is simulated by Hsim software. The main contents and research objects of this paper are as follows: firstly, this paper makes a comparative analysis of what kind of channel floating gate MOS is used in the memory cell. The reliability of P-channel floating gate MOS transistor and N-channel floating gate MOS transistor are compared, and the advantages of P communication memory cell compared with N-channel memory cell in reliability are obtained. In this paper, the P-channel floating gate MOS transistor is chosen as the memory cell. Secondly, the sensitive amplifier circuit and charge pump circuit in the peripheral circuit of Flash memory are studied. This paper analyzes the traditional circuits of these peripheral circuits, finds out their shortcomings, designs the circuits that meet the requirements, and simulates the designed circuits through Hspice. In addition, in the last chapter of this paper, the layout of the layout, routing rules, Then the IP layout design of this topic is briefly introduced. Then the whole simulation of memory is simulated and the simulation waveform of programming reading and chip erasing is analyzed emphatically.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TP333

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