本文選題：可重構(gòu)計算　切入點：粗粒度　出處：《上海交通大學(xué)》2012年碩士論文

【摘要】：隨著集成電路產(chǎn)業(yè)的不斷發(fā)展，對計算系統(tǒng)高效性和靈活性的需求也不斷增加。可重構(gòu)處理器兼具了專用集成電路的運算高效性與通用處理器的編程靈活性,近年來受到了廣泛關(guān)注�？芍貥�(gòu)處理器的典型結(jié)構(gòu)為一個主控制器耦合一個可重構(gòu)處理單元�？芍貥�(gòu)處理器的任務(wù)編譯器可以將計算任務(wù)高效地映射到可重構(gòu)處理單元中，是可重構(gòu)處理器系統(tǒng)的重要支撐軟件。 本論文針對粗粒度可重構(gòu)處理器REMUS-II，設(shè)計并實現(xiàn)了一款自動化任務(wù)編譯器LOOPCC。該任務(wù)編譯器前端部分從輸入的高級語言中自動提取被標(biāo)記的并行代碼段，將其轉(zhuǎn)化為中間表示數(shù)據(jù)流圖(DFG)。任務(wù)編譯器后端部分將DFG劃分為數(shù)個較小規(guī)模的邏輯子圖并將其映射到可重構(gòu)陣列上，最終生成驅(qū)動可重構(gòu)處理單元的配置信息和用于主控制器的配套代碼。本文采用循環(huán)部分展開技術(shù)解決了編譯前端生成DFG規(guī)模大、冗余信息多的問題。針對REMUS-II的硬件特點，本文通過使用常數(shù)輸入提取技術(shù)對DFG進(jìn)行預(yù)處理，并采用優(yōu)化陣列數(shù)據(jù)流、配置陣列循環(huán)復(fù)用等手段提高硬件資源利用率，，提高了REMUS-II可重構(gòu)處理器的運行效率。 本論文對LOOPCC進(jìn)行了功能驗證和性能分析。實驗數(shù)據(jù)表明，LOOPCC任務(wù)編譯器各項功能正確，與REMUS-II系統(tǒng)原有任務(wù)編譯器相比，編譯時間降低28%，配置信息量減少80%，同時還獲得了3倍以上的運行性能提升。
[Abstract]:With the development of integrated circuit industry, the demand for high efficiency and flexibility of computing system is increasing.Reconfigurable processors (RCPs), with both high computational efficiency of ASIC and programming flexibility of general-purpose processors, have attracted wide attention in recent years.The typical architecture of a reconfigurable processor is a master controller coupling a reconfigurable processing unit.Task compiler of reconfigurable processor can efficiently map computing task to reconfigurable processing unit, which is an important supporting software for reconfigurable processor system.In this paper, an automatic task compiler LOOPC is designed and implemented for the coarse grained reconfigurable processor REMUS-II.The front-end part of the task compiler automatically extracts the tagged parallel code segment from the input high-level language and converts it into an intermediate representation data flow graph (DFG).In the back-end part of the task compiler, the DFG is divided into several smaller logical subgraphs and mapped to the reconfigurable array, and the configuration information of the driving reconfigurable processing unit and the supporting code for the main controller are generated.In this paper, the problem of large scale and redundant information of compiling front end generated DFG is solved by using cyclic partial expansion technique.In view of the hardware characteristics of REMUS-II, this paper uses constant input extraction technology to pre-process DFG, optimizes array data flow, configures array cycle reuse and so on to improve the utilization ratio of hardware resources.The efficiency of REMUS-II reconfigurable processor is improved.In this paper, the function verification and performance analysis of LOOPCC are carried out.The experimental data show that all functions of the task compiler are correct. Compared with the original task compiler of REMUS-II system, the compilation time is reduced by 28%, the amount of configuration information is reduced by 80%, and the running performance is improved by more than 3 times.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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本文編號：1716058