基于PCIe的高速數(shù)據(jù)采集卡的FPGA設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間：2019-01-08 08:10
【摘要】：隨著數(shù)據(jù)采集系統(tǒng)的廣泛應(yīng)用，國內(nèi)與國外的技術(shù)水平仍存在一定的差距，研發(fā)一款具有自主知識產(chǎn)權(quán)的高速數(shù)據(jù)采集系統(tǒng)顯得越來越迫切，本論文課題背景是研究一款6GSPS采樣率、1GHz帶寬的高速數(shù)據(jù)采集卡，本論文主要研究的內(nèi)容是基于PCIe總線技術(shù)的高速AD采集卡的數(shù)據(jù)存儲與控制。 在硬件設(shè)計(jì)中，為了提高系統(tǒng)的采樣速率，采用兩片ADC芯片時(shí)間并行交替采樣的方法。在可編程邏輯設(shè)計(jì)中，F(xiàn)PGA作為設(shè)計(jì)的主控模塊，采用模塊化的設(shè)計(jì)思路使用VHDL語言實(shí)現(xiàn)對FPGA的控制，邏輯設(shè)計(jì)部分主要包括：基于SPI的串行通信設(shè)計(jì)實(shí)現(xiàn)時(shí)鐘芯片以及ADC芯片內(nèi)部寄存器的配置；使用FPGA內(nèi)部資源MIG控制核實(shí)現(xiàn)DDR2SDRAM高速數(shù)據(jù)的存取和讀寫控制；數(shù)據(jù)采集卡與上位機(jī)的通信采用PCIe總線接口，，使用可編程邏輯的器件Virtex5芯片生成PCIe端點(diǎn)IP核的方法實(shí)現(xiàn)，從而大大縮短了開發(fā)周期，簡化了設(shè)計(jì)流程；設(shè)計(jì)基于DMA方式的PCIe總線傳輸，數(shù)據(jù)傳輸過程中，不需要占用CPU資源卻可以實(shí)現(xiàn)更高的實(shí)際傳輸速率。 本設(shè)計(jì)和PCIe總線驅(qū)動(dòng)相結(jié)合，成功實(shí)現(xiàn)了上位機(jī)通過PCIe總線對數(shù)據(jù)采集卡各芯片的配置，也實(shí)現(xiàn)了數(shù)據(jù)采集卡向上位機(jī)傳輸AD采樣數(shù)據(jù)并存儲的功能，結(jié)合仿真軟件Modelsim和檢測FPGA內(nèi)部信號的ChipScope軟件對系統(tǒng)功能進(jìn)行調(diào)試和驗(yàn)證，從而證實(shí)了該方案的可行性。
[Abstract]:With the wide application of data acquisition system, there is still a certain gap between domestic and foreign technology level, so it is more and more urgent to develop a high-speed data acquisition system with independent intellectual property rights. The background of this thesis is to study a high speed data acquisition card with 6GSPS sampling rate and 1GHz bandwidth. The main content of this paper is the data storage and control of high speed AD acquisition card based on PCIe bus technology. In the hardware design, in order to improve the sampling rate of the system, two ADC chips were sampled in parallel. In the programmable logic design, FPGA is used as the main control module of the design, and the modular design idea is adopted to realize the control of FPGA by using VHDL language. The logic design mainly includes: the serial communication design based on SPI realizes the clock chip and the ADC chip internal register configuration; Using FPGA internal resource MIG control core to realize DDR2SDRAM high-speed data access and read and write control; The communication between the data acquisition card and the host computer adopts the PCIe bus interface, and the PCIe endpoint IP core is generated by the programmable logic device Virtex5 chip, which greatly shortens the development cycle and simplifies the design process. The PCIe bus transmission based on DMA mode is designed. In the process of data transmission, higher actual transmission rate can be achieved without taking up CPU resources. The design is combined with the PCIe bus driver, which realizes the configuration of each chip of the data acquisition card by the PCIe bus, and also realizes the function of transmitting the AD sampling data and storing the data from the data acquisition card to the host computer. The system function is debugged and verified by combining the simulation software Modelsim and the ChipScope software which detects the internal signal of FPGA, which proves the feasibility of the scheme.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP274.2
[Abstract]:With the wide application of data acquisition system, there is still a certain gap between domestic and foreign technology level, so it is more and more urgent to develop a high-speed data acquisition system with independent intellectual property rights. The background of this thesis is to study a high speed data acquisition card with 6GSPS sampling rate and 1GHz bandwidth. The main content of this paper is the data storage and control of high speed AD acquisition card based on PCIe bus technology. In the hardware design, in order to improve the sampling rate of the system, two ADC chips were sampled in parallel. In the programmable logic design, FPGA is used as the main control module of the design, and the modular design idea is adopted to realize the control of FPGA by using VHDL language. The logic design mainly includes: the serial communication design based on SPI realizes the clock chip and the ADC chip internal register configuration; Using FPGA internal resource MIG control core to realize DDR2SDRAM high-speed data access and read and write control; The communication between the data acquisition card and the host computer adopts the PCIe bus interface, and the PCIe endpoint IP core is generated by the programmable logic device Virtex5 chip, which greatly shortens the development cycle and simplifies the design process. The PCIe bus transmission based on DMA mode is designed. In the process of data transmission, higher actual transmission rate can be achieved without taking up CPU resources. The design is combined with the PCIe bus driver, which realizes the configuration of each chip of the data acquisition card by the PCIe bus, and also realizes the function of transmitting the AD sampling data and storing the data from the data acquisition card to the host computer. The system function is debugged and verified by combining the simulation software Modelsim and the ChipScope software which detects the internal signal of FPGA, which proves the feasibility of the scheme.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP274.2
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 王偉;傅其祥;;基于PCIe總線的超高速信號采集卡的設(shè)計(jì)[J];電子設(shè)計(jì)工程;2010年05期
2 呂喜在;張寶文;趙德鑫;蘇紹t
本文編號：2404335
本文鏈接：http://sikaile.net/falvlunwen/zhishichanquanfa/2404335.html
最近更新
教材專著
