發(fā)布時間：2018-04-14 14:22

  本文選題：多模多標準 + 小數(shù)頻率綜合器�。� 參考：《東南大學》2017年碩士論文

【摘要】：隨著無線通信模式的不斷涌現(xiàn),將多種通信制式集成在一個移動終端上已成為目前無線通信技術發(fā)展的趨勢,支持多模式、多標準、多頻段的射頻收發(fā)機也因此成為人們研究的熱點。而作為射頻收發(fā)機的核心組成模塊之一,頻率綜合器是決定整個收發(fā)機性能的關鍵之一。本文對多模CMOS頻率綜合器關鍵模塊及其整體優(yōu)化進行研究與設計。本文首先介紹了電荷泵鎖相環(huán)型小數(shù)頻率綜合器的基本原理和各個子模塊,推導出系統(tǒng)傳遞函數(shù)并建立線性化模型,然后根據(jù)其線性化模型分析了環(huán)路的穩(wěn)定性、動態(tài)特性和噪聲性能,并給出了小數(shù)頻率綜合器的系統(tǒng)結(jié)構(gòu)框圖。本文設計的小數(shù)分頻器主要包括高速二分頻器、可編程整數(shù)分頻器和Δ-Σ調(diào)制器。高速二分頻器采用源級耦合邏輯結(jié)構(gòu)的觸發(fā)器實現(xiàn),在進行二分頻功能的同時產(chǎn)生四相正交本振信號�？删幊陶麛�(shù)分頻器包括四分頻器和2/3分頻器鏈,其中2/3分頻器鏈采用5級2/3分頻器級聯(lián)而成,并加入邏輯門實現(xiàn)分頻比的擴展。A-Σ調(diào)制器用于實現(xiàn)量化噪聲的整形,采用了改進型MASH 1-1-1結(jié)構(gòu),可以增加輸出序列長度以減小小數(shù)雜散。本文設計的自動頻率校準單元(AFC)基于頻率比較法,主要包括最優(yōu)控制字搜索模塊和環(huán)路帶寬校準模塊。最優(yōu)控制字搜索利用二進制搜索算法和最小值存儲來實現(xiàn),環(huán)路帶寬校準則根據(jù)當前分頻比和壓控振蕩器的調(diào)諧增益來調(diào)節(jié)電荷泵電流,以實現(xiàn)環(huán)路帶寬的恒定�；诨旌闲虵IR濾波的量化噪聲抑制技術,本文對小數(shù)頻率綜合器進行了系統(tǒng)優(yōu)化設計。A-Σ調(diào)制器的輸出控制信號經(jīng)過延遲單元后,分別通過8路并行的可編程整數(shù)分頻器和鑒頻鑒相器,最后由一個8輸入可編程電荷泵在模擬域進行電荷相加�；旌闲虵IR濾波器能夠?qū)崿F(xiàn)全定制的量化噪聲整形,并且恒定的單位直流增益避免了噪聲放大的問題�；赥SMC 0.18μm RF CMOS工藝進行了電路設計和版圖設計,整個小數(shù)頻率綜合器的版圖面積為1.22x1.07mm2。其中A-∑調(diào)制器和自動頻率校準單元采用半定制設計方法,其余模塊均采用全定制設計方法。后仿真結(jié)果表明,在最差情況下小數(shù)分頻器的工作范圍為0.4～8.0GHz,分頻比范圍為32～504,最高頻率下的工作電流為7.65mA。自動頻率校準單元的校準時間約為16.2μs,頻率分辨率為5MHz,平均工作電流小于0.5mA。整個小數(shù)頻率綜合器的仿真結(jié)果表明,輸出頻率范圍為0.923～7.681GHz,頻率分辨率為20Hz,鎖定時間小于40μs,工作電流小于23mA。本次設計的小數(shù)頻率綜合器能夠滿足設計指標要求。
[Abstract]:With the continuous emergence of wireless communication modes, it has become the trend of wireless communication technology to integrate multiple communication systems on one mobile terminal, which supports multi-mode and multi-standard.Therefore, RF transceiver in multi-frequency band has become a hot research topic.As one of the core modules of RF transceiver, frequency synthesizer is one of the key factors to determine the performance of the whole transceiver.In this paper, the key modules and their overall optimization of multimode CMOS frequency synthesizer are studied and designed.In this paper, the basic principle and sub-modules of the charge pump phase-locked loop fractional frequency synthesizer are introduced, the system transfer function is derived and the linearization model is established, and then the stability of the loop is analyzed according to the linearization model.The system structure block diagram of fractional frequency synthesizer is given.The fractional divider designed in this paper mainly includes high speed dicusser, programmable integer divider and 螖-危 modulator.The high speed frequency divider is realized by the trigger with the source level coupling logic structure. The quadrature local oscillator signal is generated while the frequency division function is carried out.The programmable integer frequency divider consists of four frequency dividers and a 2 / 3 frequency divider chain, in which the 2 / 3 frequency divider chain is cascaded by a 5 stage 2 / 3 frequency divider, and an expanded. A- 危 modulator to realize the division ratio is added to realize the shaping of the quantization noise.The improved MASH 1-1-1 structure can increase the output sequence length to reduce the fractional spurious.The automatic frequency calibration unit (AFC) designed in this paper is based on the frequency comparison method, including the optimal control word search module and the loop bandwidth calibration module.The optimal control word search is realized by binary search algorithm and the minimum storage. The loop bandwidth calibration is based on the current frequency division ratio and the tuning gain of the voltage controlled oscillator to adjust the charge pump current to realize the constant bandwidth of the loop.Based on the quantization noise suppression technique of hybrid FIR filter, the output control signal of the fractional frequency synthesizer is optimized by the delay unit after the output control signal of the .A- 危 modulator is optimized.Through 8 parallel programmable integer dividers and phase discriminators, an 8-input programmable charge pump is used to add charges in analog domain.The hybrid FIR filter can realize fully customized quantization noise shaping, and the constant unit DC gain avoids the problem of noise amplification.The circuit design and layout design based on TSMC 0.18 渭 m RF CMOS process are carried out. The layout area of the whole decimal frequency synthesizer is 1.22 x 1.07mm 2.The A- 鈭，

本文編號：1749705