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  本文關鍵詞： SM4分組密碼算法 SOPC Verilog HDL NiosⅡ 串口　出處：《深圳大學》2016年碩士論文　論文類型：學位論文

【摘要】：在信息社會里,信息資源已經(jīng)成為國家、企業(yè)等團體的重要的戰(zhàn)略資源,人們對信息安全越來越重視。國家商務密碼管理中心頒布了一系列的密碼行業(yè)標準,以保護私密的數(shù)據(jù)信息和在開放鏈路中通信的數(shù)據(jù)信息。密碼行業(yè)標準中包括SM4分組密碼算法,SM4算法廣泛應用于金融卡、社保卡、無線通信、數(shù)據(jù)資料等需要對信息進行加密解密處理的領域。本文對SM4分組密碼算法進行了分析和研究,編寫SM4的C語言代碼,并進行軟件加密解密測試,以驗證分析的正確性。用Verilog HDL語言對SM4分組密碼算法進行硬件設計。并對其進行了兩種方式的測試。一種方式是在ModelSim軟件上進行仿真,編寫測試文件,產(chǎn)生激勵信號、明文、密鑰數(shù)據(jù)輸入到SM4模塊進行加密和解密操作,然后讀取加密解密的結果以驗證其正確性。由于在ModelSim上只能進行功能仿真,無法驗證SM4的時序和真實的硬件工作狀態(tài),且仿真的速度非常緩慢,進行大數(shù)據(jù)量的測試耗時非常長。因此另外一種測試方式就是結合PC快速的數(shù)據(jù)處理能力和FPGA快速硬件生成能力組建測試系統(tǒng)。首先在FPGA芯片上搭建SOPC系統(tǒng),把SM4封裝成IP模塊,嵌入到SOPC系統(tǒng)里,然后通過串口和PC相連接,組成測試系統(tǒng)。由PC產(chǎn)生大量的測試數(shù)據(jù)發(fā)送到SOPC系統(tǒng)上,SOPC系統(tǒng)接收到數(shù)據(jù)以后轉給SM4模塊,并啟動加密解密操作得到加密結果,然后SOPC再把操作結果通過串口發(fā)送回PC對結果進行判定結果是否正確。這種測試方法可以驗證SM4模塊在接近真實硬件工作狀態(tài)時,對SM4進行大數(shù)據(jù)量、長時間、高速工作狀態(tài)時的穩(wěn)定性、可靠性進行評估。從長時間測試的結果和測試速度來看(相對于ModelSim),SM4硬件模塊和搭建的測試系統(tǒng)還是成功的,但本測試系統(tǒng)也有許多不足,因為是針對SM4搭建的測試系統(tǒng),專用性太強。連接SOPC系統(tǒng)和PC的串口的通信速度最大只能達到115200bit/s,是提高測試速度的瓶頸。
[Abstract]:In the information society, information resources have become an important strategic resource of the country, enterprises and other groups. People pay more and more attention to information security. The National Business password Management Center has issued a series of cryptographic industry standards. The cryptographic industry standard includes SM4 block cipher algorithm (SM4), which is widely used in financial card, social security card and wireless communication. This paper analyzes and studies the SM4 block cipher algorithm, compiles the C language code of SM4, and carries on the software encryption and decryption test. To verify the correctness of the analysis. Use Verilog. HDL language designs the SM4 block cipher algorithm in hardware, and tests it in two ways. One way is to simulate it on ModelSim software. Write test files, generate incentive signals, plaintext, key data input to the SM4 module for encryption and decryption operations. Then read the results of encryption and decryption to verify its correctness. Because of the only functional simulation on ModelSim, it is impossible to verify the timing of SM4 and the real working state of the hardware. And the speed of simulation is very slow. It takes a lot of time to test a large amount of data, so another way of testing is to combine the fast data processing ability of PC and the fast hardware generation ability of FPGA to build a test system. First of all, the test system is built on the FPGA chip. Build SOPC system. The SM4 is encapsulated into IP module, embedded in SOPC system, and then connected with PC through serial port to form a test system. A large number of test data are generated by PC and sent to SOPC system. After receiving the data, the SOPC system transfers the data to the SM4 module and starts the encryption and decryption operation to get the encryption result. Then SOPC sends the operation result back to PC through serial port to determine whether the result is correct. This testing method can verify that the SM4 module is close to the real hardware working state. Evaluate the stability and reliability of SM4 in large amount of data, long time, high speed working condition. From the result of long time test and test speed (relative to Model Sims). SM4 hardware module and built test system is still successful, but this test system also has many shortcomings, because it is the test system built for SM4. The maximum speed of serial port communication between SOPC system and PC is 115200 bit / s, which is the bottleneck to improve the test speed.
【學位授予單位】：深圳大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN918.4

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本文編號：1468957