【摘要】：MEMS(Microelectromechanical Systems)加速度傳感器是MEMS器件中重要的一類,有著廣泛的應用,如汽車的安全性和穩(wěn)定性、生物醫(yī)學應用、石油和天然氣勘探以及電腦配件等。石油勘探最常用的方法之一就是地震勘探,在地震檢測領域,與常規(guī)檢波器相比,利用MEMS技術實現(xiàn)的檢波器具有更好的線性度和動態(tài)范圍,且具有更高的靈敏度等特點,成為目前發(fā)展主流。MEMS檢波器主要包括電容加速度傳感器和信號檢測專用集成電路芯片(Application Specific Integrated Chip,ASIC)。MEMS傳感器信號處理電路主要用來檢測MEMS電容傳感器敏感質量塊所受到的加速度,并將其轉換成電壓信號。本文主要從MEMS電容加速度傳感器電容檢測原理出發(fā),針對目前研究存在的加速度計線性度低等缺陷,結合CMOS工藝特點和已有的研究基礎,提出了二階模擬閉環(huán)力平衡反饋模式下開關電容電路檢測方案。其讀出電路主要包括電容補償陣列、參考源、多相時鐘、全差分開關電容電路、RC低通濾波和儀表放大器等。其中,全差分開關電容電路采用相關雙采樣技術消除失調,儀表放大器采用三運放結構,對差分信號進行單端輸出,具有噪聲小、精度高等特點�；谕闘50W 0.5μm工藝,針對該力平衡反饋模式對系統(tǒng)進行了時序設計,完成了讀出電路設計分析與仿真驗證、版圖設計與后仿真驗證及其流片。本文針對野外勘探ESD(Electrostatic Discharge)防護要求更為嚴苛,以及高壓ESD防護高觸發(fā)、低維持的難點,對讀出電路進行全芯片ESD防護設計,芯片的I/O端口采用互補式的柵極耦合技術的PMOS和NMOS,電源端口采用柵極耦合技術的NMOS,有效提高了芯片的ESD防護等級。整體芯片前后仿驗證均表明該系統(tǒng)具有線性度高、噪聲和失調低等特點,并在旺宏L50W 0.5μm工藝下進行流片。
[Abstract]:MEMS (Microelectromechanical Systems) accelerometer is an important class of MEMS devices, which has a wide range of applications, such as car safety and stability, biomedical applications, oil and gas exploration and computer accessories. One of the most commonly used methods for petroleum exploration is seismic exploration. In the field of seismic detection, compared with the conventional geophone, the geophone realized by MEMS technology has better linearity and dynamic range, and has higher sensitivity and so on. MEMS geophone mainly includes capacitive acceleration sensor and signal detection chip (Application Specific Integrated Chip,ASIC). MEMS sensor signal processing circuit, which is mainly used to detect the acceleration of the sensitive mass block of MEMS capacitive sensor. And convert it into a voltage signal. Based on the principle of capacitance detection of MEMS capacitive accelerometer, this paper aims at the defects of low linearity of accelerometer, combining with the characteristics of CMOS process and the existing research foundation. In this paper, a second order analog closed loop force balance feedback detection scheme for switched capacitor circuits is proposed. The readout circuit includes capacitor compensation array, reference source, polyphase clock, fully differential switched capacitor circuit, RC low-pass filter and instrument amplifier. Among them, the fully differential switched capacitor circuit uses correlation double sampling technology to eliminate the misalignment, and the instrument amplifier adopts a three-stage operational amplifier structure, which outputs the differential signal with a single end, which has the characteristics of low noise and high precision. Based on Wanghong L50W 0.5 渭 m process, the timing design of the system is carried out for the force balance feedback mode. The readout circuit design analysis and simulation verification, layout design and post simulation verification and flow sheet are completed. Aiming at the more severe requirements of field exploration ESD (Electrostatic Discharge) protection, and the difficulties of high trigger and low maintenance of high voltage ESD protection, the whole chip ESD protection design of readout circuit is carried out in this paper. The I / O port of the chip adopts the complementary gate coupling technology PMOS and the NMOS, power port adopts the gate coupling technology NMOS, to effectively improve the ESD protection level of the chip. The simulation results show that the system has the characteristics of high linearity, low noise and misalignment, and the flow sheet is carried out in Wanghong L50W 0.5 渭 m process.
【學位授予單位】：湘潭大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TP212

【參考文獻】

相關碩士學位論文 前3條

1 李樂樂;低功耗、高精度、寬共模輸入范圍儀表放大器的研究與設計[D];復旦大學;2013年

2 張文杰;MEMS加速度傳感器讀出電路設計[D];湘潭大學;2013年

3 林麗娟;基于20V NLDMOS結構的ESD防護器件的設計[D];電子科技大學;2012年

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本文編號：2292762