無線通信中的高階QAM實現(xiàn)技術研究
發(fā)布時間：2019-06-28 16:16
【摘要】：4G時代,人們對移動通信和便攜式通信的關注度越來越高。隨著通信業(yè)務范圍的不斷擴大,數據量幾乎呈爆炸增長態(tài)勢,面對日益緊張的頻譜資源,傳統(tǒng)調制方式已經難以滿足當前通信需求。QAM調制因頻譜利用率高、抗干擾能力強等優(yōu)點而廣泛應用于各種有線通信、無線通信場合。本文主要研究高階QAM的實現(xiàn)技術,并以無線通信為背景,在64QAM業(yè)務模式下完成整個通信系統(tǒng)的軟硬件仿真、設計、實現(xiàn)以及測試等任務。其中,基帶部分在FGPA中以全數字方式實現(xiàn),射頻部分借助AD9361軟件無線電平臺實現(xiàn),具體研究工作如下:首先,設計系統(tǒng)傳輸方案,并在Simulink環(huán)境下搭建仿真模型,驗證方案的可行性。針對收發(fā)機中的各子模塊,本文給出了詳細的原理設計和仿真結果。然后,將仿真模型在FPGA中定點實現(xiàn),并在確定量化精度后,按照模塊化設計原則分別在ISE和Modelsim中進行代碼編寫與功能仿真。對設計中的一些關鍵模塊本文采取了相關優(yōu)化措施,比如時鐘部分采用全局時鐘管理技術,保證時鐘的同源同相性;載波同步算法和盲均衡算法設計時,選擇雙模式切換算法,并使用高頻時鐘作為計算時鐘,從而加快算法收斂速度,提高系統(tǒng)通信效率。最后,利用Xilinx公司的ML605開發(fā)板和ADI公司的AD9361板卡完成硬件調試與系統(tǒng)測試工作,這部分是設計的重點也是難點。本文通過在PC端編寫上位機軟件實現(xiàn)對AD9361硬件平臺的靈活配置功能,并在調試期間,根據晶振校準系數、數據時鐘延遲等實際硬件特性不斷調整配置參數,優(yōu)化系統(tǒng)性能;數據接口設計時本文選擇了高速LVDS傳輸模式,有效降低了噪聲信號干擾,利用FPGA內部的IDDR和ODDR原語可以完成差分信號的邊沿轉換和數據重組工作。硬件調試結束之后,分別在Cable信道和Wireless信道下,完成64QAM信號的系統(tǒng)測試任務。最終的測試結果表明,系統(tǒng)各模塊的邏輯設計與功能完全正確,本文在FPGA上較好地完成了64QAM通信系統(tǒng)的設計與實現(xiàn)任務。
[Abstract]:In the 4G era, people's attention to mobile communication and portable communication is getting higher and higher. With the expansion of the business scope of communication, the data volume is almost explosive, and in the face of the increasing frequency of spectrum resources, the traditional modulation method has been difficult to meet the current communication requirement. The QAM modulation is widely applied to various wired communication and wireless communication occasions due to the advantages of high spectrum utilization rate, strong anti-interference capability and the like. In this paper, the realization technology of high-order QAM is mainly studied, and the hardware and software simulation, design, implementation and test of the whole communication system are carried out in the 64 QAM service mode with the background of wireless communication. The baseband part is implemented in full-digital manner in the FGPA, and the RF part is implemented by the AD9361 software radio platform. The specific research work is as follows: First, the system transmission scheme is designed, and the simulation model is set up in the Simulink environment, and the feasibility of the scheme is verified. For each sub-module in the transceiver, the detailed principle design and simulation results are given in this paper. Then, the simulation model is realized at a fixed point in the FPGA, and after the quantization precision is determined, the code writing and the function simulation are carried out in the ISE and the Modelsim according to the modular design principle, respectively. Some key modules in the design have adopted relevant optimization measures, such as the use of global clock management technology in the clock part, and guarantee the homophase of the clock; when the carrier synchronization algorithm and the blind equalization algorithm are designed, the dual-mode switching algorithm is selected, And the high-frequency clock is used as the calculation clock, so that the convergence speed of the algorithm is accelerated, and the communication efficiency of the system is improved. Finally, using the ML605 development board of Xilinx and the AD9361 board of Analog Devices to complete the hardware debugging and system testing, this part is the focus of the design. In this paper, the flexible configuration function of the AD9361 hardware platform is realized by writing the upper computer software at the PC end, and the configuration parameters are constantly adjusted according to the actual hardware characteristics such as the crystal oscillator calibration coefficient and the data clock delay during the debugging, and the system performance is optimized; In the design of the data interface, the high-speed LVDS transmission mode is selected, the interference of the noise signal is effectively reduced, and the edge conversion and the data recombination of the differential signal can be completed by using the IDDR and ODDR primitives inside the FPGA. After the end of the hardware debugging, the system test task of the 64QAM signal is completed under the Cable and Wireless channels, respectively. The final test results show that the logic design and function of each module of the system are completely correct, and the design and implementation tasks of the 64QAM communication system are well completed in the FPGA.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN92
本文編號：2507440
[Abstract]:In the 4G era, people's attention to mobile communication and portable communication is getting higher and higher. With the expansion of the business scope of communication, the data volume is almost explosive, and in the face of the increasing frequency of spectrum resources, the traditional modulation method has been difficult to meet the current communication requirement. The QAM modulation is widely applied to various wired communication and wireless communication occasions due to the advantages of high spectrum utilization rate, strong anti-interference capability and the like. In this paper, the realization technology of high-order QAM is mainly studied, and the hardware and software simulation, design, implementation and test of the whole communication system are carried out in the 64 QAM service mode with the background of wireless communication. The baseband part is implemented in full-digital manner in the FGPA, and the RF part is implemented by the AD9361 software radio platform. The specific research work is as follows: First, the system transmission scheme is designed, and the simulation model is set up in the Simulink environment, and the feasibility of the scheme is verified. For each sub-module in the transceiver, the detailed principle design and simulation results are given in this paper. Then, the simulation model is realized at a fixed point in the FPGA, and after the quantization precision is determined, the code writing and the function simulation are carried out in the ISE and the Modelsim according to the modular design principle, respectively. Some key modules in the design have adopted relevant optimization measures, such as the use of global clock management technology in the clock part, and guarantee the homophase of the clock; when the carrier synchronization algorithm and the blind equalization algorithm are designed, the dual-mode switching algorithm is selected, And the high-frequency clock is used as the calculation clock, so that the convergence speed of the algorithm is accelerated, and the communication efficiency of the system is improved. Finally, using the ML605 development board of Xilinx and the AD9361 board of Analog Devices to complete the hardware debugging and system testing, this part is the focus of the design. In this paper, the flexible configuration function of the AD9361 hardware platform is realized by writing the upper computer software at the PC end, and the configuration parameters are constantly adjusted according to the actual hardware characteristics such as the crystal oscillator calibration coefficient and the data clock delay during the debugging, and the system performance is optimized; In the design of the data interface, the high-speed LVDS transmission mode is selected, the interference of the noise signal is effectively reduced, and the edge conversion and the data recombination of the differential signal can be completed by using the IDDR and ODDR primitives inside the FPGA. After the end of the hardware debugging, the system test task of the 64QAM signal is completed under the Cable and Wireless channels, respectively. The final test results show that the logic design and function of each module of the system are completely correct, and the design and implementation tasks of the 64QAM communication system are well completed in the FPGA.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN92
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