【摘要】：直接序列擴(kuò)頻通信由于其出色抗干擾能力、頻帶利用率和保密性,近年來被廣泛的應(yīng)用到軍事和民用領(lǐng)域。本論文設(shè)計(jì)的通信系統(tǒng),采用大規(guī)模可編程邏輯器件(FPGA),所設(shè)計(jì)與實(shí)現(xiàn)的擴(kuò)頻通信系統(tǒng)的發(fā)射端、接收端,各模塊,包括重要的載波發(fā)生器(NCO)、各種濾波器、及數(shù)字環(huán)路濾波器、鎖相環(huán)等各模塊,都集成在一個(gè)FPGA芯片上,提高了通信系統(tǒng)的穩(wěn)定性與可靠性。本文研究了現(xiàn)有的擴(kuò)頻算法,完成了發(fā)送端、接收端各個(gè)模塊的設(shè)計(jì)與調(diào)試,具體所做的工作如下:(1)結(jié)合FPGA的特點(diǎn),對現(xiàn)有的擴(kuò)頻碼同步方法進(jìn)行了優(yōu)化和改進(jìn),提出了一種便于FPGA器件實(shí)現(xiàn)的PN碼同步方法,最終完成信號的解擴(kuò)�？拱自肼暷芰蛇_(dá)-25.38 dB,抗單頻噪聲干擾能力可達(dá)-18.3dB。(2)在載波同步電路的設(shè)計(jì)中,對傳統(tǒng)的Costas環(huán)結(jié)構(gòu)進(jìn)行了改進(jìn),經(jīng)過試驗(yàn)測試,節(jié)省了資源提高了同步電路的可靠性。(3)在位同步電路的設(shè)計(jì)中。結(jié)合傳統(tǒng)的加扣時(shí)鐘位同步、Gardner位同步算法,提出了一種“基于跳變檢測調(diào)整頻率字”的位同步算法。該算法精度介于上述兩者之間,結(jié)合了鎖相環(huán)具有的良好跟蹤、記憶性能,結(jié)構(gòu)簡單便于實(shí)現(xiàn)。是一種面向判決的位同步提取算法,更適用于FPGA器件的硬件電路實(shí)現(xiàn)。(4)通過RS232串口實(shí)現(xiàn)了計(jì)算機(jī)產(chǎn)生的基帶信號源與FPGA開發(fā)板的調(diào)制及解調(diào)系統(tǒng)的數(shù)據(jù)通信接口設(shè)計(jì),該接口設(shè)計(jì)可移植性好,便于對通信系統(tǒng)的性能進(jìn)行測試。
[Abstract]:Direct sequence spread spectrum communication has been widely used in military and civil fields in recent years because of its excellent anti-interference ability, band efficiency and confidentiality. The communication system designed in this paper adopts the transmitter, receiver and modules of the spread spectrum communication system designed and implemented by large-scale programmable logic device (FPGA), including all kinds of filters of important carrier generator (NCO),. And digital loop filter, phase-locked loop and other modules are integrated on a FPGA chip, which improves the stability and reliability of the communication system. In this paper, the existing spread spectrum algorithms are studied, and the design and debugging of each module at the transmitter and receiver are completed. The specific work is as follows: (1) according to the characteristics of FPGA, the existing spread spectrum code synchronization methods are optimized and improved. In this paper, a PN code synchronization method is proposed, which is convenient for FPGA devices to realize, and finally the signal despreading is completed. The anti-white noise ability of-25.38 dB, is up to-18.3 dB. (2) in the design of carrier synchronization circuit, the traditional Costas ring structure is improved and tested. The resources are saved and the reliability of the synchronization circuit is improved. (3) in the design of the in-place synchronization circuit. Combined with the traditional clock synchronization and Gardner bit synchronization algorithm, a bit synchronization algorithm based on jump detection and frequency word adjustment is proposed. The accuracy of the algorithm is between the above two, which combines the good tracking and memory performance of the phase-locked loop, and the structure is simple and easy to implement. It is a bit synchronization extraction algorithm for decision, which is more suitable for the hardware circuit implementation of FPGA devices. (4) the data communication interface between the baseband signal source generated by computer and the modulation and demodulation system of FPGA development board is designed through RS232 serial port. The interface design has good portability and is convenient to test the performance of communication system.
【學(xué)位授予單位】：青島大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN914.42

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本文編號：2491086