【摘要】：視頻編解碼技術(shù)在數(shù)字高清電視、網(wǎng)絡(luò)流媒體、視頻通信等領(lǐng)域廣泛應(yīng)用,目前主流的標(biāo)準(zhǔn)是2003.3正式發(fā)布的H.264/AVC與2013.1正式發(fā)布的HEVC/H.265�，F(xiàn)存大量H.264標(biāo)準(zhǔn)的視頻文件,且相較HEVC, H.264的解碼算法復(fù)雜度更低一些,本文選擇H.264眾核解碼做為研究起點(diǎn)。H.264標(biāo)準(zhǔn)為保證高畫質(zhì)、低碼率,需要進(jìn)行大量的計(jì)算,目前H.264解碼方案主要有高性能CPU/DSP方案、硬件加速專用模塊、專用ASIC芯片/FPGA方案、多核(2/4核、ARM+DSP結(jié)構(gòu))方案,各方案在性能、功耗、靈活性方面各有優(yōu)缺點(diǎn)。本文面向H.264視頻解碼應(yīng)用,研究高性能、低功耗、高靈活性的H.264視頻眾核(16核及以上)解碼實(shí)現(xiàn)方案,探索解決H.264眾核解碼中的關(guān)鍵技術(shù)問(wèn)題,所得結(jié)果亦可用于H.265及其他視頻標(biāo)準(zhǔn)。目標(biāo)眾核平臺(tái)是由MCVP-NoC系統(tǒng)構(gòu)建生成的虛擬平臺(tái)。MCVP-NoC是自行設(shè)計(jì)的支持定制NoC (Networks-on-Chip,片上網(wǎng)絡(luò))的多核虛擬平臺(tái)建模工具,它采用“SystemC + TLM2.0 + OVP”工具構(gòu)建,MCVP-NoC生成的虛擬平臺(tái)能運(yùn)行實(shí)際程序,支持真實(shí)應(yīng)用驅(qū)動(dòng),可用于項(xiàng)目早期軟件開發(fā)、調(diào)試,系統(tǒng)架構(gòu)探索,以及性能、功耗、面積評(píng)估等。本文的主要工作有:(1)分析H.264解碼計(jì)算性能瓶頸;(2) H.264解碼的任務(wù)劃分與眾核映射。先按解碼流程進(jìn)行任務(wù)劃分,采用“碼流分析、slice解碼、濾波、輸出”四級(jí)流水,再對(duì)解碼流程各部分按計(jì)算量劃分,進(jìn)行多核并行加速。(3)構(gòu)建眾核虛擬平臺(tái),用其運(yùn)行H.264眾核解碼程序,評(píng)測(cè)性能。眾核系統(tǒng)采用4x4 2D mesh結(jié)構(gòu),共16個(gè)處理器節(jié)點(diǎn),每個(gè)節(jié)點(diǎn)含1個(gè)orlk處理器、32M字節(jié)指令存儲(chǔ)器、32M字節(jié)數(shù)據(jù)存儲(chǔ)器,所有節(jié)點(diǎn)共享1個(gè)256M字節(jié)shared-memory。該模型可運(yùn)行實(shí)際H.264解碼代碼,能定量分析性能,可用于系統(tǒng)架構(gòu)優(yōu)化、片上存儲(chǔ)需求分析,存儲(chǔ)方案優(yōu)化;能定量分析核間通信流量,可用于指導(dǎo)核間NoC互聯(lián)結(jié)構(gòu)與鏈路帶寬設(shè)計(jì)。
[Abstract]:Video coding and decoding technology is widely used in digital HDTV, network streaming media, video communication and so on. At present, the main standard is H.264 / AVC which was officially released in 2003.3 and HEVC / H.265which was officially released in 2013.1. There are a large number of H.264 standard video files, and the complexity of H.264 decoding algorithm is lower than that of HEVC, H.264 decoding is chosen as the research starting point. H.264 standard is used to guarantee high quality and low bit-rate, it needs a lot of calculation. At present, H.264 decoding schemes mainly have high performance CPU / DSP scheme, special hardware acceleration module, ASIC chip / FPGA scheme and multi-core (2 / 4 core arm DSP structure) scheme. Each scheme has its own advantages and disadvantages in performance, power consumption and flexibility. For H.264 video decoding applications, this paper studies the implementation scheme of H.264 video multi-core (16 cores and above) with high performance, low power consumption and high flexibility, and explores the key technical problems in H.264 video decoding. The results can also be used in H. 265 and other video standards. The target multi-core platform is a virtual platform built by MCVP-NoC system. MCVP-NoC is a multi-core virtual platform modeling tool designed by itself to support customized Noc (Networks-on-Chip). It uses "system C TLM2.0 OVP" tool to build virtual platform generated by MCVP-NoC, which can run actual program, support real application driver, and can be used in early software development, debugging, system architecture exploration, performance, power consumption, area evaluation and so on. The main work of this paper is as follows: (1) analyzing the bottleneck of H. 264 decoding computing performance; (2) mapping the task partition of H. 264 decoding and the map-core. First, the task is divided according to the decoding flow, and then the multi-core parallel acceleration is carried out according to the calculation amount of each part of the decoding process, and the "stream analysis slice decoding, filtering, output" four-level pipeline is adopted. (3) the multi-core virtual platform is constructed, and the multi-core virtual platform is constructed. Use it to run H.264 core decoding program to evaluate the performance. The multi-core system uses 4x4 2D mesh structure, 16 processor nodes, each node contains one orlk processor 32m byte instruction memory 32 megabyte data memory, all nodes share a 256m byte shared-memory. The model can run actual H.264 decoding code, can quantitatively analyze performance, can be used for system architecture optimization, on-chip storage requirement analysis, storage scheme optimization, and quantitative analysis of inter-core communication traffic. It can be used to guide the design of NOC interconnection structure and link bandwidth between cores.
【學(xué)位授予單位】：山東科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN919.81

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