本文選題：高速調(diào)制解調(diào) + APSK�。� 參考：《哈爾濱工業(yè)大學(xué)》2017年碩士論文

【摘要】：隨著衛(wèi)星通信技術(shù)的不斷進(jìn)步,為了滿足衛(wèi)星通信中日益增長(zhǎng)的數(shù)據(jù)傳輸需求,高速調(diào)制解調(diào)技術(shù)在軍事民用領(lǐng)域都具有很高的價(jià)值。本文對(duì)適用于衛(wèi)星通信的16APSK調(diào)制解調(diào)器設(shè)計(jì)與實(shí)現(xiàn)進(jìn)行深入研究,主要研究?jī)?nèi)容集中在高階調(diào)制方式研究、高速并行架構(gòu)設(shè)計(jì)、16APSK調(diào)制器的設(shè)計(jì)、16APSK解調(diào)器的設(shè)計(jì)幾個(gè)方面。首先介紹了高速調(diào)制解調(diào)器的研究意義,國(guó)內(nèi)外對(duì)衛(wèi)星通信調(diào)制解調(diào)器的研究現(xiàn)狀及發(fā)展趨勢(shì)。隨后研究了衛(wèi)星通信中非線性信道特點(diǎn),結(jié)合誤碼性能及實(shí)現(xiàn)復(fù)雜度,選擇16APSK作為本文衛(wèi)星通信中的通信體制。比較了三種已有的高速并行處理架構(gòu)的優(yōu)缺點(diǎn),重點(diǎn)分析了調(diào)制解調(diào)器的理論基礎(chǔ),包括調(diào)制器和解調(diào)器的基本原理、數(shù)學(xué)模型及結(jié)構(gòu),并研究了調(diào)制解調(diào)器中成型匹配濾波、載波恢復(fù)、位同步及頻率合成技術(shù)等關(guān)鍵技術(shù)。其次,對(duì)16APSK的星座圖進(jìn)行了優(yōu)化設(shè)計(jì),將4+12-ASPK星座圖中內(nèi)外圓的半徑比選取為2.7,使其具有最佳的抗干擾性能。為了降低數(shù)據(jù)處理速率,以APRX結(jié)構(gòu)為基礎(chǔ)設(shè)計(jì)了調(diào)制解調(diào)器的全并行結(jié)構(gòu)。重點(diǎn)研究了全并行高速調(diào)制解調(diào)技術(shù),在調(diào)制器部分,主要研究了多相結(jié)構(gòu)的并行成型濾波和采用了并行NCO的上變頻技術(shù)。在解調(diào)器部分,研究了時(shí)域并行和頻域并行兩種匹配濾波結(jié)構(gòu),并對(duì)比了兩者計(jì)算復(fù)雜度;比較了超前滯后門法、Gardner算法,研究了Gardner位同步環(huán)路,設(shè)計(jì)了并行位同步方案;研究了DD、極性判決等載波恢復(fù)算法,提出了一種改進(jìn)的聯(lián)合載波恢復(fù)技術(shù),環(huán)路具有更大的載波頻偏捕獲范圍和更穩(wěn)定的跟蹤性能,并設(shè)計(jì)了并行載波恢復(fù)方案;研究了串并轉(zhuǎn)換時(shí)的偏移調(diào)整技術(shù),設(shè)計(jì)了并行結(jié)構(gòu)的高速數(shù)據(jù)接口。最后,在Xilinx平臺(tái)上對(duì)信息速率為100Mbps的高速16APSK調(diào)制解調(diào)器進(jìn)行設(shè)計(jì)與實(shí)現(xiàn)。詳細(xì)闡述了16APSK高速調(diào)制器和解調(diào)器中主要功能模塊的設(shè)計(jì)方法和調(diào)試結(jié)果,包括調(diào)制器中的多相結(jié)構(gòu)并行成型濾波模塊和并行NCO上變頻模塊,解調(diào)器中的時(shí)域并行匹配濾波模塊、并行Gardner位同步模塊、并行載波恢復(fù)模塊等,并對(duì)各功能模塊工作的正確性進(jìn)行了驗(yàn)證。
[Abstract]:With the development of satellite communication technology, in order to meet the increasing demand of data transmission in satellite communication, high-speed modulation and demodulation technology is of great value in military and civilian fields. In this paper, the design and implementation of 16APSK modem suitable for satellite communication are deeply studied. The research focuses on the high order modulation mode and the design of the high speed parallel architecture modulator / 16APSK demodulator. Firstly, the research significance of high-speed modem, the research status and development trend of satellite communication modem at home and abroad are introduced. Then, the characteristics of nonlinear channel in satellite communication are studied. Combined with the error performance and complexity, 16APSK is chosen as the communication scheme in this paper. The advantages and disadvantages of three existing high-speed parallel processing architectures are compared, and the theoretical basis of modem is analyzed, including the basic principle of modulator and demodulator, mathematical model and structure, and the shaping matched filter in modem is studied. Carrier recovery, bit synchronization and frequency synthesis technology and other key technologies. Secondly, the 16APSK constellation diagram is optimized, and the radius ratio of the inner and outer circle in the 4 12-ASPK constellation diagram is chosen to be 2.7, which makes it have the best anti-interference performance. In order to reduce the data processing rate, the full parallel structure of modem is designed based on APRX architecture. The full parallel high speed modulation and demodulation technology is mainly studied. In the modulator part, the parallel shaping filter with polyphase structure and the up-conversion technology using parallel NCO are mainly studied. In the part of demodulator, two kinds of parallel filtering structures in time domain and frequency domain are studied, and the computational complexity of them is compared, and the Gardner bit synchronization loop is studied, and the parallel bit synchronization scheme is designed. In this paper, the DDD, polarity decision and other carrier recovery algorithms are studied, and an improved joint carrier recovery technique is proposed. The loop has a larger carrier offset acquisition range and a more stable tracking performance, and a parallel carrier recovery scheme is designed. The offset adjustment technique in serial-parallel conversion is studied, and a high speed data interface with parallel structure is designed. Finally, a high speed 16APSK modem with 100Mbps information rate is designed and implemented on Xilinx platform. The design method and debugging results of the main function modules in the 16APSK high speed modulator and demodulator are described in detail, including the multiphase structure parallel shaping filter module and the parallel NCO up-conversion module. The time domain parallel matched filter module, parallel Gardner bit synchronization module, parallel carrier recovery module and so on are included in the demodulator. The correctness of each functional module is verified.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN927.2;TN915.05

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