本文選題：HEVC + 視頻編碼��； 參考：《哈爾濱工業(yè)大學》2017年碩士論文

【摘要】：相比于H.264視頻壓縮標準,近期提出的新標準HEVC(High Efficiency Video Coding),在以增加計算復雜度為代價的前提下,壓縮效率提高了近50%。與此同時,復雜的算法也需要更好的設計方法來迎接高視頻分辨率帶來的挑戰(zhàn)。因此,對HEVC標準中的各部分功能的進一步優(yōu)化具有非常重要的有意義。幀內預測作為HEVC的一個重要組成部分,通過利用位于當前編碼單元的左方以及上方的相鄰參考像素得到當前塊的重建塊的過程。幀內預測的復雜性主要體現在編碼單元結構靈活性的增長和預測模式數量的增加。在參考模型HM中,采用了一種靈活的四叉樹塊劃分結構對編碼單元進行分割,根據不同區(qū)域紋理復雜度的不同,對于復雜度較高的預測單元采用較小的塊進行預測編碼,反之采用較大的塊進行編碼,在預測和轉換編碼過程中進一步提高效率,同時在進行模式選擇時為所有預測單元定義了35種模式。本課題主要對HEVC幀內預測中編碼單元的劃分方式以及預測單元的模式選擇兩個方面展開研究。本文的主要研究內容包括HEVC幀內預測算法的HM實現和FPGA實現。本文利用Sobel算子對HEVC中編碼單元進行劃分以及對預測單元的模式選擇進行判斷,在HM中對算法進行驗證。HM中的實現主要對編碼時間、率失真性能等方面進行測試,并與HEVC標準進行比較,驗證算法的優(yōu)越性。幀內預測算法在FPGA上的實現用到了Xilinx Virtex6 ML605開發(fā)板,通過WinDriver驅動ML605板卡,在Win Driver生成的應用層程序的調控下,圖像數據利用PCIE接口的DMA控制器從上位機傳入FPGA,接下來對導入的圖像數據進行幀內預測處理,最后將得到的預測圖像數據通過DMA傳送回上位機,并用MATLAB對圖像數據進行譯碼后觀察處理結果。幀內預測算法的FPGA實現包括數據的存儲、圖像劃分、模式選擇、參考像素的處理、變換、量化、反變化、反量化等模塊的Verilog HDL實現。實驗結果表明,相對HEVC標準,HEVC幀內預測算法進行優(yōu)化后,在保證圖像質量及壓縮效率的同時,編碼時間有了大幅度的減少,并且完成了HEVC幀內預測算法的FPGA實現對圖像進行壓縮處理。
[Abstract]:Compared with H.264 video compression standard, the recently proposed new standard HEVC(High Efficiency Video coding improves the compression efficiency by nearly 50% at the cost of increasing computational complexity.At the same time, complex algorithms also need better design methods to meet the challenges of high video resolution.Therefore, it is very important to optimize the function of each part of HEVC standard.Intra-frame prediction is an important part of HEVC. The reconstruction block of the current block is obtained by using adjacent reference pixels located on the left side of the current coding unit as well as adjacent reference pixels above the current coding unit.The complexity of intra prediction is mainly reflected in the increase of coding unit structure flexibility and the increase in the number of prediction modes.In the reference model HM, a flexible quadtree block partition structure is used to segment the coding unit. According to the different texture complexity of different regions, the prediction unit with high complexity is predicted by smaller blocks.On the contrary, large blocks are used for coding, which can further improve the efficiency in the prediction and conversion coding process. At the same time, 35 patterns are defined for all prediction units in the process of mode selection.In this paper, the division of coding units in HEVC intra prediction and the mode selection of prediction units are studied.The main contents of this paper include HM implementation and FPGA implementation of HEVC intra prediction algorithm.In this paper, the coding unit in HEVC is divided by Sobel operator and the mode selection of prediction unit is judged. The implementation of the algorithm in HM is mainly tested on coding time, rate-distortion performance and so on.Compared with HEVC standard, the superiority of the algorithm is verified.The implementation of intra prediction algorithm on FPGA uses the Xilinx Virtex6 ML605 development board, which drives the ML605 card through WinDriver, under the control of the application layer program generated by Win Driver.The image data is passed into FPGA by the DMA controller of PCIE interface, then the imported image data is processed by intra prediction. Finally, the predicted image data is transmitted back to the host computer through DMA.The image data is decoded by MATLAB and the results are observed and processed.The FPGA implementation of intra prediction algorithm includes data storage, image partition, mode selection, processing of reference pixels, transformation, quantization, inverse change, inverse quantization and Verilog HDL implementation.The experimental results show that compared with the HEVC standard, the coding time is greatly reduced while the image quality and compression efficiency are guaranteed.And the FPGA implementation of HEVC intra prediction algorithm is completed.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN919.81;TN791

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本文編號：1773020