發(fā)布時間：2018-03-25 17:10

  本文選題：數(shù)字下變頻　切入點：軟件無線電　出處：《山東大學》2016年碩士論文

【摘要】：在當今國內無線通信系統(tǒng)中,數(shù)字接收機由于受到前端A／D轉換器的采樣速率、購買渠道和后端數(shù)字基帶數(shù)據模塊處理速度的限制,一般情況下會把從天饋系統(tǒng)接收到的射頻信號先經過模擬正交混頻轉換成合適的低中頻信號,然后在中頻部分進行數(shù)字下變頻處理,經過數(shù)據采集、數(shù)字正交混頻、抽取、整形濾波等把中頻信號轉換為低速的零中頻信號后,再送給后續(xù)的基帶模塊進行數(shù)字AGC、時鐘同步、均衡、載波恢復、解調、譯碼等數(shù)據處理,這樣可以解決由于器件本身采樣速率和處理時鐘的限制造成的后續(xù)設計困難,因此數(shù)字下變頻的設計和實現(xiàn)在現(xiàn)代無線通信領域中具有十分重要的實用意義。當前無線通信設備中,高密度、高性能以及低功耗的FPGA芯片逐漸取代了一些價格昂貴的專用集成電路,采用FPGA電路設計可以利用通用的硬件設計平臺,降低硬件電路設計的復雜度,在軟件升級、單元互聯(lián)、調試測試方面都有很大的優(yōu)勢。本論文在信號采樣原理、數(shù)控振蕩器、正交混頻、數(shù)字濾波器等相關理論的基礎上,分析研究了FPGA實現(xiàn)數(shù)字下變頻技術的可行性,并在通用的硬件平臺上得到驗證。本課題的主要工作包括以下幾點：第一、對數(shù)字下變頻技術相關的基本理論作了詳細的敘述,對專用DDC芯片和FPGA實現(xiàn)數(shù)字下變頻進行比較,給出基于FPGA實現(xiàn)數(shù)字下變頻的優(yōu)勢。第二、從硬件電路和軟件兩個方面詳細介紹了數(shù)字下變頻的設計與實現(xiàn)方法。硬件電路詳細介紹了本課題的通用硬件平臺,對各個電路模塊進行了詳細的原理說明；軟件部分給出實現(xiàn)數(shù)字下變頻的流程框圖和其中關鍵模塊設計方法。第三、通過FPGA芯片(Altera公司的Stratix Ⅳ系列)對數(shù)字下變頻各個模塊進行驗證,給出測試和仿真結果。
[Abstract]:In the domestic wireless communication system nowadays, the digital receiver is limited by the sampling rate of the front-end A / D converter, the purchasing channel and the processing speed of the back-end digital baseband data module. In general, the RF signals received from the sky feed system will be converted into appropriate low intermediate frequency signals through analogue orthogonal mixing, and then digital down-conversion processing will be carried out in the intermediate frequency section. After data acquisition, digital orthogonal mixing and decimation, After converting the intermediate frequency signal into a low speed zero intermediate frequency signal, the shaping and filtering process is then sent to the subsequent baseband module for digital AGCs, clock synchronization, equalization, carrier recovery, demodulation, decoding and other data processing. In this way, the difficulty of subsequent design caused by the limitation of sampling rate and processing clock of the device itself can be solved. Therefore, the design and implementation of digital down-conversion is of great practical significance in the field of modern wireless communication. FPGA chips with high performance and low power consumption have gradually replaced some expensive ASIC. Using FPGA circuit design can make use of general hardware design platform, reduce the complexity of hardware circuit design, upgrade software, interconnect units. On the basis of the theory of signal sampling, numerical control oscillator, orthogonal mixing, digital filter and so on, the feasibility of realizing digital downconversion with FPGA is analyzed. The main work of this paper is as follows: first, the basic theory of digital down-conversion technology is described in detail, and the comparison between the dedicated DDC chip and the realization of digital down-conversion by FPGA is carried out. The advantages of digital down conversion based on FPGA are given. Secondly, the design and implementation of digital down conversion are introduced in detail from the aspects of hardware circuit and software. The hardware circuit introduces the general hardware platform of this subject in detail. The principle of each circuit module is explained in detail. The flow chart and the key module design method are given in the software part. Each module of digital down-conversion is verified by Stratix 鈪，

本文編號：1664071