發(fā)布時(shí)間：2018-03-19 09:03

  本文選題：信道極化　切入點(diǎn)：極化碼　出處：《南京航空航天大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：自從A.E Shannon提出Shannon定理以來,探尋能夠達(dá)到Shannon極限的信道編碼一直是通信領(lǐng)域的研究熱點(diǎn)。近幾十年來,兩大接近Shannon極限的信道編碼Turbo碼和LDPC碼日趨成熟,并已在現(xiàn)代通信中得到了廣泛應(yīng)用。隨著土耳其教授Ardal Arikan基于信道極化現(xiàn)象提出極化碼,極化碼的研究腳步一刻也沒有停止過。極化碼有著線性的編碼和譯碼復(fù)雜度和優(yōu)越的性能,所以對(duì)于極化碼的研究極具現(xiàn)實(shí)意義。本文旨在基于信道極化現(xiàn)象對(duì)極化碼的性質(zhì)以及編譯碼方法進(jìn)行深入研究,并給出了一種基于FPGA的SCL譯碼器設(shè)計(jì),主要的研究內(nèi)容和創(chuàng)新點(diǎn)如下:(1)研究了Turbo碼和LDPC碼的基本編譯碼原理,并與極化碼的基本編譯碼方法進(jìn)行了宏觀比較,說明各自的優(yōu)缺點(diǎn)。通過對(duì)BEC和BSC等特定信道的組合和拆分,研究了信道極化現(xiàn)象的產(chǎn)生及性質(zhì),且不失一般性,可運(yùn)用于AWGN信道等通信系統(tǒng)中的常見信道。(2)研究了極化碼是如何基于極化現(xiàn)象產(chǎn)生的,在此基礎(chǔ)上產(chǎn)生了極化碼生成矩陣的迭代方法。重點(diǎn)對(duì)極化碼SC、SCL、CA-SCL、BP等譯碼算法進(jìn)行研究,通過仿真分析不同條件下的譯碼性能。信道挑選是極化碼理論中極為重要的分支,本文在對(duì)現(xiàn)有經(jīng)典信道挑選方法進(jìn)行總結(jié)的同時(shí)提出一種AWGN信道下的新方法。該方法根據(jù)AWGN信道特性將其轉(zhuǎn)化為BSC信道,再由BSC信道的巴式參數(shù)完成信道挑選。仿真表明,該方法在高信噪比情況下優(yōu)于傳統(tǒng)方法。(3)研究了適合硬件實(shí)現(xiàn)的最小和算法,并針對(duì)不同的量化寬度使用最小和算法進(jìn)行性能仿真,最終對(duì)LLR進(jìn)行8比特量化處理,而路徑度量值采用12比特量化�？偨Y(jié)了SC譯碼器硬件結(jié)構(gòu)的演進(jìn)發(fā)展過程,在此基礎(chǔ)上為了減少系統(tǒng)資源的消耗,基于半并行結(jié)構(gòu)提出了一種單計(jì)算單元的譯碼結(jié)構(gòu),并運(yùn)用于本文的SCL譯碼器硬件設(shè)計(jì)中。詳細(xì)介紹了本設(shè)計(jì)中各個(gè)子模塊的功能,并使用Verilog語言在EDA工具QuartusⅡ上編寫模塊,然后調(diào)用Modelsim對(duì)程序進(jìn)行了RTL級(jí)仿真。在系統(tǒng)時(shí)鐘頻率為300MHz的情況下,譯碼器的吞吐率可達(dá)6.24Mbps,資源利用率僅為6%。
[Abstract]:Since A.E Shannon put forward the Shannon theorem, it has been a hot topic in the field of communication to explore the channel coding that can reach the Shannon limit. In recent decades, two channel codes, Turbo code and LDPC code, which are close to the Shannon limit, have become more and more mature. And has been widely used in modern communication. With the introduction of polarization codes based on channel polarization phenomenon by Ardal Arikan in Turkey, The study of polarimetric codes has not stopped for a moment. Polarization codes have linear coding and decoding complexity and superior performance. Therefore, the study of polarization codes is of great practical significance. Based on the polarization phenomenon of the channel, the properties and encoding and decoding methods of polarization codes are studied in this paper, and a design of SCL decoder based on FPGA is presented. The main research contents and innovations are as follows: (1) the basic encoding and decoding principles of Turbo and LDPC codes are studied and compared with the basic encoding and decoding methods of polarimetric codes. By combining and splitting specific channels such as BEC and BSC, the generation and properties of channel polarization are studied, and the characteristics of polarization are studied without loss of generality. In this paper, we study how polarization codes are generated based on polarization phenomena, and then produce iterative method of polarization code generation matrix. The channel selection is an important branch of polarization code theory. In this paper, we summarize the existing classical channel selection methods and propose a new method under AWGN channel, which is converted to BSC channel according to the characteristics of AWGN channel, and then selected by the parameters of BSC channel. The simulation results show that, In the case of high SNR, this method is superior to the traditional method. It studies the minimum sum algorithm suitable for hardware implementation, and simulates the performance of the minimum sum algorithm for different quantization widths. Finally, the LLR is processed with 8-bit quantization. In order to reduce the consumption of system resources, a decoding structure of single computing unit is proposed based on the semi-parallel structure in order to reduce the consumption of system resources, and the evolution of the hardware structure of SC decoder is summarized. It is used in the hardware design of SCL decoder in this paper. The function of each sub-module in this design is introduced in detail, and the module is written on the EDA tool Quartus 鈪，

本文編號(hào)：1633578