發(fā)布時(shí)間：2018-03-13 07:06

  本文選題：HEVC　切入點(diǎn)：幀內(nèi)預(yù)測　出處：《合肥工業(yè)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：新一代視頻編解碼HEVC/H.265是ITU-T的視頻編碼專家組和ISO/IEC的動(dòng)態(tài)圖像專家組聯(lián)合提出最新視頻編碼標(biāo)準(zhǔn)。與H.264相比,HEVC碼流雖然減少50%,但是編解碼端復(fù)雜度大大增加。本文首先研究HEVC幀內(nèi)預(yù)測和變換模塊的算法,然后結(jié)合硬件設(shè)計(jì)特點(diǎn),對(duì)算法進(jìn)行優(yōu)化,最后根據(jù)優(yōu)化后的算法進(jìn)行VLSI設(shè)計(jì)。本文主要工作如下:1、HEVC幀內(nèi)預(yù)測模塊硬件電路設(shè)計(jì)針對(duì)幀內(nèi)預(yù)測硬件架構(gòu)電路面積較大、工作頻率較低等問題,對(duì)三種預(yù)測模式(DC預(yù)測、Planar預(yù)測以及角度預(yù)測)分別開展優(yōu)化設(shè)計(jì)。首先對(duì)幀內(nèi)預(yù)測算法進(jìn)行優(yōu)化,然后使用模塊復(fù)用以及寄存器緩存等技術(shù)對(duì)DC預(yù)測模式硬件電路進(jìn)行優(yōu)化;采用模塊復(fù)用以及狀態(tài)機(jī)跳轉(zhuǎn)等方法對(duì)Planar預(yù)測模式硬件電路進(jìn)行優(yōu)化;使用查找表以及專用乘法器模塊等技術(shù)對(duì)角度預(yù)測模式硬件電路進(jìn)行優(yōu)化。實(shí)驗(yàn)結(jié)果表明,與優(yōu)化前相比,DC預(yù)測模式硬件電路在頻率上提升40%,在邏輯門上減少32.4%,在處理延時(shí)上減少50%; Planar預(yù)測模式在工作頻率上提升62%,在電路面積上減少51%,在處理延時(shí)上減少25%;角度預(yù)測模式電路在硬件效率上提升176%。2、HEVC變換模塊硬件電路設(shè)計(jì)針對(duì)變換模塊中DST算法硬件設(shè)計(jì)中存在的頻率較慢、電路面積較大的問題,設(shè)計(jì)優(yōu)化DST硬件電路。首先結(jié)合DST矩陣系數(shù)運(yùn)算數(shù)值特點(diǎn),提出一種改進(jìn)的DST算法;在此基礎(chǔ)上,本文設(shè)計(jì)對(duì)應(yīng)于該算法專用乘法器,并通過轉(zhuǎn)置緩存器以及流水線等方法,對(duì)電路的性能進(jìn)行提升。由實(shí)驗(yàn)可得,與優(yōu)化前相比,本文設(shè)計(jì)電路在電路面積上減少25.07%,在功耗上節(jié)省33.36%。
[Abstract]:The new generation video coding and decoding HEVC/H.265 is the latest video coding standard proposed by ITU-T video coding expert group and ISO/IEC dynamic image expert group. Compared with H. 264, the video stream is reduced by 50%, but the complexity of encoding and decoding end is greatly increased. Firstly, the algorithm of intra prediction and transform module in HEVC is studied. Then according to the characteristics of hardware design, the algorithm is optimized, and finally the VLSI is designed according to the optimized algorithm. The main work of this paper is as follows: 1. In order to solve the problem of low working frequency, three kinds of prediction modes, such as DC prediction, Planar prediction and angle prediction, are optimized. First of all, the intra prediction algorithm is optimized. Then the hardware circuit of DC prediction mode is optimized by module reuse and register buffer, and the hardware circuit of Planar prediction mode is optimized by module reuse and state machine jump. The hardware circuit of angle prediction mode is optimized by using lookup table and special multiplier module. The experimental results show that, Compared with before optimization, the hardware circuit of DC predictive mode is 40% higher in frequency, 32.4 in logic gate and 50 in processing delay; Planar prediction mode increases 62% in working frequency, 51th less in circuit area, and 51% in processing delay. The hardware circuit design of the DST transform module based on the angle prediction mode circuit improves the hardware efficiency of 1760.2HEVC transform module. The frequency in the hardware design of the DST algorithm in the transform module is relatively slow. In order to solve the problem of large circuit area, the DST hardware circuit is designed and optimized. Firstly, an improved DST algorithm is proposed according to the numerical characteristics of DST matrix coefficient operation, and then a special multiplier corresponding to this algorithm is designed in this paper. By means of transposing buffer and pipeline, the performance of the circuit is improved. The experimental results show that the circuit designed in this paper reduces the area of the circuit by 25.07 and saves 33.36 in power consumption.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN919.81

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本文編號(hào)：1605304