【摘要】：針對(duì)傳統(tǒng)高斯濾波算法硬件設(shè)計(jì)方法中關(guān)鍵路徑較長(zhǎng)、邏輯延時(shí)較大的問題,提出加數(shù)壓縮的硬件優(yōu)化實(shí)現(xiàn)方法.在高斯濾波算法優(yōu)化實(shí)現(xiàn)過程中,采用移位操作來實(shí)現(xiàn)乘法與除法計(jì)算,避免使用乘法器與除法器.并引入保留進(jìn)位加法器(CSA)、基于多路選擇器(MUX)的4-2壓縮器、加數(shù)壓縮的樹型結(jié)構(gòu),對(duì)9個(gè)加數(shù)進(jìn)行3個(gè)層次的壓縮.經(jīng)過優(yōu)化后,只需1個(gè)全加器便可得求和結(jié)果.結(jié)果表明,經(jīng)過加數(shù)壓縮設(shè)計(jì)可以達(dá)到縮短關(guān)鍵路徑、減少邏輯延時(shí)的目標(biāo),使邏輯延時(shí)縮小32.48%,同時(shí)還極大節(jié)省所需加法器宏單元數(shù),為后續(xù)圖像處理模塊提供更大的設(shè)計(jì)自由度.
[Abstract]:Aiming at the problem of long critical path and long logic delay in the hardware design of traditional Gao Si filtering algorithm, a hardware optimization method of additive compression is proposed. In the process of optimization and implementation of Gao Si filtering algorithm, the shift operation is used to realize multiplication and division calculation, and the multiplier and divider are avoided. The 4-2 compressor based on the multiplexer (MUX) is introduced into the reserved carry adder (CSA), and the tree structure of addition compression is introduced to compress nine additions at three levels. After optimization, only one full adder is needed to obtain the summation result. The results show that after the addition compression design, the key path can be shortened, the logical delay can be reduced by 32.48, and the number of macro cells of the adder can be greatly saved. For the subsequent image processing module to provide a greater degree of freedom.
【作者單位】： 浙江大學(xué)電氣工程學(xué)院;展訊科技(杭州)有限公司;
【基金】：國(guó)家“863”高技術(shù)研究發(fā)展計(jì)劃資助項(xiàng)目(2012AA041701)
【分類號(hào)】：TN713;TP391.41
，

本文編號(hào)：2207694