本文選題：人臉識(shí)別 + 卷積神經(jīng)網(wǎng)絡(luò)　； 參考：《西安理工大學(xué)》2017年碩士論文

【摘要】：隨著計(jì)算機(jī)科學(xué)和互聯(lián)網(wǎng)技術(shù)的快速發(fā)展,人臉識(shí)別技術(shù)廣泛的應(yīng)用于如公共安全,公安、司法和刑偵,信息安全和門禁系統(tǒng)等各種領(lǐng)域,比如公安領(lǐng)域需要在系統(tǒng)人臉庫(kù)中找出罪犯的相關(guān)信息,或在門禁系統(tǒng)中快速識(shí)別和匹配相關(guān)人員的身份信息。人臉作為穩(wěn)定的、直觀的、辨識(shí)度高的生物特性受到研究者愈來(lái)愈多的重視。本文對(duì)識(shí)別人數(shù)較小場(chǎng)合下的人臉識(shí)別進(jìn)行研究,分析了各類人臉識(shí)別算法及優(yōu)缺點(diǎn)后選擇深度學(xué)習(xí)中卷積神經(jīng)網(wǎng)絡(luò)實(shí)現(xiàn)人臉識(shí)別。首先介紹了卷積神經(jīng)網(wǎng)絡(luò)的相關(guān)原理,然后分析了經(jīng)典激活函數(shù)的特性。研究表明卷積神經(jīng)網(wǎng)絡(luò)中參數(shù)擁有大量的冗余度,選擇雙曲正切(tanh)作為激活函數(shù)時(shí),網(wǎng)絡(luò)中神經(jīng)元激活數(shù)目太多,而修正線性單元(ReLU)激活函數(shù)雖然擁有稀疏激活特性,但是由于本文根據(jù)識(shí)別人數(shù)的限定設(shè)計(jì)出的網(wǎng)絡(luò)卷積層層數(shù)為4, ReLU激活函數(shù)響應(yīng)邊為線性的特性在網(wǎng)絡(luò)較小的情況下對(duì)數(shù)據(jù)擬合效果很差。本文綜合兩個(gè)激活函數(shù)的特性提出一種新的激活函數(shù)(newfuc),該激活函數(shù)具有一定程度的稀疏激活特性和非線性響應(yīng)特征。在本文實(shí)驗(yàn)中對(duì)ORL人臉庫(kù)、FERET人臉庫(kù)和Yalefaces人臉庫(kù)訓(xùn)練結(jié)果表示,在網(wǎng)絡(luò)參數(shù)冗余度高的情況下,該激活函數(shù)比原激活函數(shù)具有更高的識(shí)別率,而且由于引入稀疏性,減輕了原網(wǎng)絡(luò)參數(shù)的冗余度和算法的計(jì)算復(fù)雜度。由于卷積神經(jīng)網(wǎng)絡(luò)算法的并行性,硬件實(shí)現(xiàn)方式能夠通過(guò)增加硬件資源,同時(shí)進(jìn)行多個(gè)運(yùn)算單元的計(jì)算,加速其計(jì)算過(guò)程。本文詳細(xì)設(shè)計(jì)了基于卷積神經(jīng)網(wǎng)絡(luò)的人臉識(shí)別算法的硬件模塊,首先將整個(gè)算法主要?jiǎng)澐譃榭刂颇K、卷積采樣模塊、全連接模塊和分類輸出模塊,其中卷積采樣模塊和全連接層模塊提取人臉特征,分類輸出模塊對(duì)特征分類后輸出人臉類別,控制模塊協(xié)調(diào)整個(gè)硬件的正常運(yùn)行。然后對(duì)每個(gè)模塊用verilog語(yǔ)言進(jìn)行RTL級(jí)描述,并用Modelsim軟件進(jìn)行功能仿真。驗(yàn)證設(shè)計(jì)邏輯功能正確并在Quartus II工具綜合后下載到FPGA開(kāi)發(fā)板,在開(kāi)發(fā)板上驗(yàn)證了算法硬件實(shí)現(xiàn)的正確性和可行性。
[Abstract]:With the rapid development of computer science and Internet technology, face recognition technology is widely used in various fields such as public security, justice and criminal investigation, information security and access control system. For example, the public security field needs to find the relevant information of criminals in the system face database, or to identify and match the identity information of the relevant persons in the access control system. As a stable, intuitive and highly recognizable biological feature, face has attracted more and more attention. In this paper, face recognition with small number of people is studied, and all kinds of face recognition algorithms and convolution neural network in depth learning are analyzed to realize face recognition. Firstly, the principle of convolution neural network is introduced, and then the characteristic of classical activation function is analyzed. The results show that the parameters in the convolution neural network have a lot of redundancy. When the hyperbolic tangent tanh) is chosen as the activation function, the number of neurons in the network is too much, while the modified linear unit (ReLU) activation function has the characteristics of sparse activation. However, because the network convolution layer number is 4, the response edge of ReLU activation function is linear, and the effect of data fitting is very poor when the network is small. In this paper, a new activation function is proposed based on the properties of the two activation functions. The activation function has the characteristics of sparse activation and nonlinear response to a certain extent. In this experiment, the training results of ORL face database and Yalefaces face database show that the activation function has a higher recognition rate than the original activation function under the condition of high redundancy of network parameters, and because of the introduction of sparsity. The redundancy of the original network parameters and the computational complexity of the algorithm are reduced. Due to the parallelism of the convolution neural network algorithm, the hardware implementation can speed up the computing process by increasing the hardware resources and computing several computing units simultaneously. In this paper, the hardware module of face recognition algorithm based on convolution neural network is designed in detail. Firstly, the whole algorithm is divided into control module, convolution sampling module, full connection module and classification output module. The convolutional sampling module and the full connection layer module extract face features, and the classification output module outputs face categories after classifying the features, and the control module coordinates the normal operation of the whole hardware. Then each module is described at RTL level with verilog language, and the function is simulated by Modelsim software. The logic function of the design is verified and downloaded to the FPGA development board after the synthesis of Quartus II tools. The correctness and feasibility of the algorithm hardware implementation are verified on the development board.
【學(xué)位授予單位】：西安理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP391.41;TP183

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本文編號(hào)：1895084