As a computing paradigm that combines temporal and spatial computations, dynamic reconfigurable computing provides superiorities of flexibility, energy efficiency and area efficiency, attracting interest from both academia and industry.However, dynamic reconfigurable computing is not yet mature because of several unsolved problems. This work introduces the concept, architecture, and compilation techniques of dynamic reconfigurable computing. It also discusses the existing major challenges and po... 

【文章來源】：Journal of Semiconductors. 2020,41(02)CSCD

【文章頁數(shù)】：10 頁

【文章目錄】：
1. Introduction
2. Architecture
    2.1. Architecture model
    2.2. Reconfigurable controller
    2.3. Reconfigurable datapath
    2.4. Configuration
    2.5. Implementation instance:HReA
3. Compilation
    3.1. The compiler’s framework
    3.2. Key techniques for compiling
        3.2.1. Code transformation and optimization
        3.2.2. Temporal task partition
        3.2.3. Internal memory management
        3.2.4. Configuration optimization
4. Challenges
    4.1. Cooperation of temporal and spatial mapping
    4.2. Control-intensive task parallelization
    4.3. Optimization of configuration organization
    4.4. Dynamically loading configuration
5. Applications
    5.1. Neural network
    5.2. Cryptography
    5.3. Multimedia
    5.4. Signal processing
6. Conclusion


【參考文獻(xiàn)】：
期刊論文
[1]Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture[J]. WANG YanSheng,LIU LeiBo,YIN ShouYi,ZHU Min,CAO Peng,YANG Jun,WEI ShaoJun.  Science China（Information Sciences）. 2013(11)
[2]可重構(gòu)媒體處理器任務(wù)編譯器的前端設(shè)計(jì)[J]. 殷崇勇,尹首一,劉雷波,楊超,朱敏,魏少軍.  北京郵電大學(xué)學(xué)報(bào). 2011(03)



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