本文選題：單粒子翻轉(zhuǎn)　切入點(diǎn)：單粒子瞬態(tài)　出處：《合肥工業(yè)大學(xué)》2016年碩士論文

【摘要】：單粒子效應(yīng)是引發(fā)航天器異常的主要原因。在數(shù)字電路中單粒子效應(yīng)主要包括單粒子翻轉(zhuǎn)(SEU)和單粒子瞬態(tài)(SET),前者發(fā)生在時(shí)序元件中,表現(xiàn)為邏輯狀態(tài)的翻轉(zhuǎn)；后者發(fā)生在組合邏輯和時(shí)鐘電路中,表現(xiàn)為瞬態(tài)脈沖。它們都可能形成軟錯(cuò)誤,影響電路的可靠性。隨著工藝進(jìn)入納米尺度,器件尺寸和供電電壓不斷下降,SEU和SET變得更加嚴(yán)重；而且時(shí)鐘頻率不斷上升,組合邏輯中的SET轉(zhuǎn)化為軟錯(cuò)誤的概率也在增加。因此,如何設(shè)計(jì)抗SEU和SET的集成電路成為迫切需要解決的問題。本論文研究抗SEU和SET的加固設(shè)計(jì)方法,旨在提高電路的可靠性。目前,已有的加固設(shè)計(jì)主要集中在防護(hù)SEU和(或)組合邏輯中的SET,不能防護(hù)時(shí)鐘電路中的SET；而且加固成本比較大,影響電路的性能和開銷,不利于實(shí)際應(yīng)用。抗SET的方法通常是在組合邏輯末端使用過濾電路,如時(shí)間冗余電路、施密特觸發(fā)器和CVSL門。抗SEU的方法有硬件冗余、分離節(jié)點(diǎn)、檢錯(cuò)糾錯(cuò)和切斷反饋環(huán)。同時(shí)抗SEU/SET的方法有時(shí)間冗余與硬件冗余的結(jié)合(如TR-TMR和TR-HLR電路),以及包含延遲單元的鎖存器(如FERST和LSEH-1鎖存器)�；赟MIC 65nm CMOS工藝,本論文提出一種單粒子加固鎖存器設(shè)計(jì)。該鎖存器使用延遲單元和級(jí)聯(lián)C單元構(gòu)建時(shí)間冗余,屏蔽從組合邏輯傳播而來的SET。由于采用了嵌入式延遲單元,該鎖存器能夠容忍時(shí)鐘信號(hào)上的SET。當(dāng)內(nèi)部節(jié)點(diǎn)受單個(gè)粒子轟擊而發(fā)生邏輯翻轉(zhuǎn),C單元進(jìn)入保持狀態(tài)以避免整個(gè)鎖存器受影響,抑制SEU。Hspice仿真結(jié)果表明,相比已有的加固設(shè)計(jì),該鎖存器不存在共模故障敏感節(jié)點(diǎn),還能容忍時(shí)鐘電路中的SET；版圖面積、功耗和時(shí)鐘電路功耗分別平均下降30.58%、44.53%和26.51%；而且該鎖存器的功耗對(duì)工藝、供電電壓和溫度的波動(dòng)不敏感。
[Abstract]:Single particle effect is the main cause of spacecraft anomaly. In digital circuit, single particle effect mainly includes single particle flip (set) and single particle transient set (the former occurs in time series element and is represented as logic state reversal; The latter occurs in combinational logic and clock circuits and is characterized by transient pulses. Both of them may result in soft errors that affect the reliability of the circuit. The device size and the supply voltage are falling. The SEU and SET become more serious; and the clock frequency is rising, and the probability of SET conversion into soft error in combinational logic is also increasing. How to design an integrated circuit that resists SEU and SET becomes an urgent problem to be solved. In this paper, the reinforcement design method of anti-#en2# and SET is studied in order to improve the reliability of the circuit. The existing reinforcement design is mainly focused on the protection of set in SEU and / or combination logic, but not on the set in clock circuit, and the cost of reinforcement is relatively high, which affects the performance and cost of the circuit. The method of resisting SET is to use filter circuits at the end of combinational logic, such as time redundancy circuit, Schmitt flip-flop and CVSL gate. At the same time, the method of resisting SEU/SET includes the combination of time redundancy and hardware redundancy (such as TR-TMR and TR-HLR circuit, and latch containing delay unit, such as FERST and LSEH-1 latch). Based on SMIC 65nm CMOS process, In this paper, a single particle reinforced latch design is proposed. The latch uses delay elements and cascaded C elements to build time redundancy and shield SETs propagating from combinational logic. The latch can tolerate the set on the clock signal. When the internal node is bombarded by a single particle, the logic flip C unit enters the holding state to avoid the whole latch from being affected. The simulation results of suppressing SEU.Hspice show that, compared with the existing reinforcement design, The latch has no common mode fault sensitive node and can tolerate the set in the clock circuit. The layout area, power consumption and clock circuit power consumption are reduced by 30.58% 44.53% and 26.51% respectively, and the power consumption of the latch is insensitive to the fluctuation of technology, supply voltage and temperature.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：V442

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