本文選題：移動支付 + 高性能　； 參考：《華中科技大學》2015年碩士論文

【摘要】：近場支付基于近距離無線通信技術(shù),能夠方便的應(yīng)用于手機、PDA、平板電腦等嵌入式智能設(shè)備,在目前國內(nèi)主流的進場支付方案中,SWP接口就是SIM卡與CLF前端芯片之間的單線全雙工通信接口。首先,SWP接口使用單線全雙工通信,需要在電路中實現(xiàn)雙向信號調(diào)制,將收、發(fā)信號合成到單線上,達到減少芯片管腳使用的目的,并且電路規(guī)模不能太復(fù)雜,這樣既符合SIM卡的尺寸規(guī)范,又實現(xiàn)了NFC功能的擴展。其次,SWP接口需要在短時間內(nèi)傳輸大量數(shù)據(jù),因此SWP接口的通信性能是本設(shè)計中必須重視的一點。在系統(tǒng)設(shè)計方面,將SWP接口電路掛載到高吞吐率的AHB總線上,為SWP電路設(shè)計了專用的DMA通道。另外,在基帶信號處理時,實現(xiàn)了全并行數(shù)據(jù)收發(fā)和通信速率自適應(yīng)。本設(shè)計在后文的FPGA評估中表明,電路面積375SLICE單元,通信速率達到1Mbps,有效數(shù)據(jù)244.14Kbyte/s,相對于UART串行接口的通信速率19.2Kbps,有效數(shù)據(jù)2.34Kbyte/s,性能有明顯優(yōu)勢。再次,SWP接口應(yīng)用于移動嵌入式平臺,對電路低功耗要求較高。因此設(shè)計了低功耗的狀態(tài)控制器,能夠?qū)崟r的切換電路工作模式。并且在系統(tǒng)設(shè)計中加入了時鐘管理模塊,在電路邏輯綜合中加入了自動門控模式,通過這些方法降低了電路功耗。在后文的功耗評估中可知,SWP工作在低功耗模式時的功耗幾乎為零,正常工作時在1.2mw左右。國外SWP接口IP價格昂貴,且購買方無自主知識產(chǎn)權(quán)。國內(nèi)部分公司設(shè)計的SWP接口電路規(guī)模較大,電路結(jié)構(gòu)復(fù)雜。本文SWP接口基于SMIC 130nm PFLASH工藝,電路面積為10K個等校門,成功流片后使用MP300測試儀進行測試,測試結(jié)果表明本文SWP接口通信速率達到1Mbps,無數(shù)據(jù)丟包、誤碼等現(xiàn)象。
[Abstract]:Near field payment is based on close range wireless communication technology. It can be conveniently applied to embedded intelligent devices such as mobile phone, PDA, tablet computer and so on. In the current domestic mainstream payment scheme, the SWP interface is a single line full duplex communication interface between SIM card and CLF front end chip. First, the SWP interface uses single line full duplex communication and needs to be in the circuit In this way, bidirectional signal modulation is realized, the receiving and sending signal is synthesized on the single line to reduce the use of the chip foot, and the circuit size can not be too complex. This not only conforms to the size specification of the SIM card, but also realizes the expansion of the NFC function. Secondly, the SWP interface needs to transmit a large amount of data in a short time, so the communication performance of the SWP interface is this In the design of the system, the SWP interface circuit is mounted on the high throughput AHB bus, and a special DMA channel is designed for the SWP circuit. In addition, the full parallel data transceiver and the communication rate adaptive are realized when the baseband signal is processed. This design shows the circuit area 375SLICE single in the FPGA evaluation of the later text. The communication rate is 1Mbps, the effective data is 244.14Kbyte/s, the communication rate of the UART serial interface is 19.2Kbps, the effective data 2.34Kbyte/s, the performance has the obvious advantage. Again, the SWP interface is applied to the mobile embedded platform, and the low power demand of the circuit is higher. Therefore, the low power state controller is designed, and the real-time switching circuit can be designed. The clock management module is added to the system design, and the automatic gate control mode is added to the logic synthesis of the circuit. The power consumption of the circuit is reduced by these methods. The power consumption of SWP in the low power consumption mode is almost zero at the low power consumption mode, and it is working at about 1.2MW at the normal working time. The foreign SWP interface IP price is high. The SWP interface circuit designed by some domestic companies is large and the circuit structure is complex. The SWP interface is based on the SMIC 130nm PFLASH technology and the circuit area is 10K. After the successful flow sheet, the MP300 tester is used to test it. The test results show that the communication rate of SWP interface reaches 1Mbps, numerous and numerous. According to a packet loss, a bit of error, and so on.

【學位授予單位】：華中科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

【參考文獻】

相關(guān)期刊論文 前7條

1 王篤炎;肖海;何平;;基于NFC-SWP技術(shù)的移動支付方案設(shè)計[J];移動通信;2013年05期

2 劉玉軍;申曄;符銳;賈峻;;SWP/HCI協(xié)議棧測試研究[J];中國集成電路;2011年04期

3 劉浩;;基于NFC技術(shù)的近場通信應(yīng)用探索[J];中國無線電;2010年12期

4 李菁;;手機支付在我國移動電子商務(wù)中的應(yīng)用[J];電腦與電信;2010年05期

5 韓麗英;陳紹強;;近距離通信的SWP方案及在SIM卡中的實現(xiàn)方法[J];單片機與嵌入式系統(tǒng)應(yīng)用;2010年03期

6 石亦欣;李蔚;;NFC芯片與SIM卡連接的方案研究[J];中國集成電路;2007年07期

7 李建昌,趙博生,鮑勝榮,鐘銳;基于ARM7TDMI的SoC芯片的FPGA驗證平臺設(shè)計[J];電子工程師;2004年09期

相關(guān)碩士學位論文 前8條

1 董琦;基于Android平臺的NFC終端設(shè)計[D];電子科技大學;2013年

2 戴爾O，

本文編號：1786498