本文關(guān)鍵詞：基于SoCs結(jié)構(gòu)的測試訪問機制的研究與實現(xiàn)　出處：《哈爾濱理工大學》2015年碩士論文　論文類型：學位論文

  更多相關(guān)文章： SoCs測試結(jié)構(gòu) 多級測試訪問機制 測試策略 測試封裝設(shè)計

【摘要】：集成電路制造技術(shù)工藝的極速發(fā)展促使嵌入式系統(tǒng)芯片的廣泛應用，通過IP核復用技術(shù)將不同功能模塊集成到一塊芯片上被稱為稱為片上系統(tǒng)，即微系統(tǒng)芯片SoC。同時，電路集成規(guī)模和復雜程度的提高以及IP核種類的多樣性，使得SoC芯片的可測性實現(xiàn)和測試策略的實施成為棘手的問題。近年來，為解決SoC測試面積消耗過大和測試時間過長的問題，提出了SoCs測試結(jié)構(gòu)，即在SoC中嵌套SoC構(gòu)成SoCs。在SoCs測試結(jié)構(gòu)下，一方面，要設(shè)計有效的測試封裝結(jié)構(gòu)實現(xiàn)IP核的可測性，同時要盡量減少寄存器單元的數(shù)量，從而減小測試中的面積消耗進而縮短SoC整體測試時間；另一方面，對SoC和SoCs的測試訪問機制TAM進行科學劃分，對有限的TAM資源進行合理分配，通過資源復用等策略實行分組并行測試，已成為SoC的測試亟需解決的問題。因此，就要對SoCs測試結(jié)構(gòu)的測試策略進行研究，為緩解今后日益復雜的超大規(guī)模集成電路昂貴的測試開銷提供可借鑒的方法。 本文中，以ITC’02測試基準電路SoC d695為基礎(chǔ)，建立SoCs系統(tǒng)芯片的層次化測試結(jié)構(gòu)模型。借鑒毫微程序控制器思想，，以宏命令為先導，運用軟硬件協(xié)同設(shè)計的思想對測試結(jié)構(gòu)模型進行設(shè)計與優(yōu)化，設(shè)計相應的多級測試訪問機制。在該層次化測試結(jié)構(gòu)下，以傳統(tǒng)SoC測試中單級測試訪問機制的實現(xiàn)方法為依托，根據(jù)掃描測試技術(shù)原理以及IEEE1500測試標準，綜合考慮芯核測試外殼的功能實現(xiàn)、核內(nèi)掃描鏈平衡優(yōu)化以及測試總線劃分等原則進行SoCs并行測試單元Wrapper設(shè)計、SoCs多級測試訪問機制TAM設(shè)計，提出了SoCs組式帶寬靈活分配TAM測試策略。在測試調(diào)度控制時，采用宏模塊控制的思想加以實現(xiàn)。將SoCs層次化測試結(jié)構(gòu)分而治之、并行測試，增加了測試的靈活性，從而提高測試效率，節(jié)約測試時間，對目前日益復雜化的層次型SoCs的可測試實現(xiàn)與優(yōu)化研究具有很大的現(xiàn)實意義。
[Abstract]:Application of integrated circuit manufacturing technology to speed the development of the embedded system chip, through the IP reuse technology of different functional modules are integrated into a chip called called system on chip, micro chip SoC. system at the same time, the scale and complexity of integrated circuit and the improvement of the IP nuclear diversity makes can implement and test the implementation of the strategy has become the difficult problem of measuring SoC chip. In recent years, in order to solve the SoC test area of excessive consumption and long test time of the problem, put forward SoCs test structure, which is nested in SoC SoC SoCs. on the one hand, SoCs test structure, and to test the package structure design the realization of the testability of the IP core, and try to reduce the number of register unit, thereby reducing the test area consumption and shorten the overall test time of SoC; on the other hand, the SoC and SoCs test to visit TAM asked the mechanism of scientific classification, rational allocation of limited TAM resources, grouping parallel test through the implementation of resource reuse strategy has become urgent to solve the problem of the SoC test. Therefore, we should test strategy for SoCs test structure is studied, which may provide reference for alleviating the cost of testing large scale integrated circuit in the future increasingly complex and expensive.
In this paper, the ITC 02 benchmark circuits SoC d695 based hierarchical structure model test SoCs system chip. Using microprogram controller, with macro command as the guide, using the hardware and software co design ideas for the design and optimization of test model, design the appropriate multi-level test access mechanism in the. The hierarchical structure with a single level test, test access mechanism of traditional SoC test implementation method as the basis, according to the principle of scanning test and IEEE1500 test standard, considering the shell core test functions, SoCs parallel test unit Wrapper design of nuclear scan chain balance optimization and test bus division principle, multistage SoCs test access mechanism of TAM design, proposed the SoCs group type flexible bandwidth allocation TAM test strategy. In the test scheduling control, using macro module control theory to realize The SoCs hierarchical test structure is divided and governed. Parallel testing increases the flexibility of testing, improves testing efficiency and saves test time. It has great practical significance for the test and optimization of SoCs, which is becoming more and more complex.

【學位授予單位】：哈爾濱理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN407

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