本文關(guān)鍵詞：基于SoCs結(jié)構(gòu)的測(cè)試訪問(wèn)機(jī)制的研究與實(shí)現(xiàn)　出處：《哈爾濱理工大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： SoCs測(cè)試結(jié)構(gòu) 多級(jí)測(cè)試訪問(wèn)機(jī)制 測(cè)試策略 測(cè)試封裝設(shè)計(jì)

【摘要】：集成電路制造技術(shù)工藝的極速發(fā)展促使嵌入式系統(tǒng)芯片的廣泛應(yīng)用，通過(guò)IP核復(fù)用技術(shù)將不同功能模塊集成到一塊芯片上被稱為稱為片上系統(tǒng)，即微系統(tǒng)芯片SoC。同時(shí)，電路集成規(guī)模和復(fù)雜程度的提高以及IP核種類的多樣性，使得SoC芯片的可測(cè)性實(shí)現(xiàn)和測(cè)試策略的實(shí)施成為棘手的問(wèn)題。近年來(lái)，為解決SoC測(cè)試面積消耗過(guò)大和測(cè)試時(shí)間過(guò)長(zhǎng)的問(wèn)題，提出了SoCs測(cè)試結(jié)構(gòu)，即在SoC中嵌套SoC構(gòu)成SoCs。在SoCs測(cè)試結(jié)構(gòu)下，一方面，要設(shè)計(jì)有效的測(cè)試封裝結(jié)構(gòu)實(shí)現(xiàn)IP核的可測(cè)性，同時(shí)要盡量減少寄存器單元的數(shù)量，從而減小測(cè)試中的面積消耗進(jìn)而縮短SoC整體測(cè)試時(shí)間；另一方面，對(duì)SoC和SoCs的測(cè)試訪問(wèn)機(jī)制TAM進(jìn)行科學(xué)劃分，對(duì)有限的TAM資源進(jìn)行合理分配，通過(guò)資源復(fù)用等策略實(shí)行分組并行測(cè)試，已成為SoC的測(cè)試亟需解決的問(wèn)題。因此，就要對(duì)SoCs測(cè)試結(jié)構(gòu)的測(cè)試策略進(jìn)行研究，為緩解今后日益復(fù)雜的超大規(guī)模集成電路昂貴的測(cè)試開(kāi)銷提供可借鑒的方法。 本文中，以ITC’02測(cè)試基準(zhǔn)電路SoC d695為基礎(chǔ)，建立SoCs系統(tǒng)芯片的層次化測(cè)試結(jié)構(gòu)模型。借鑒毫微程序控制器思想，，以宏命令為先導(dǎo)，運(yùn)用軟硬件協(xié)同設(shè)計(jì)的思想對(duì)測(cè)試結(jié)構(gòu)模型進(jìn)行設(shè)計(jì)與優(yōu)化，設(shè)計(jì)相應(yīng)的多級(jí)測(cè)試訪問(wèn)機(jī)制。在該層次化測(cè)試結(jié)構(gòu)下，以傳統(tǒng)SoC測(cè)試中單級(jí)測(cè)試訪問(wèn)機(jī)制的實(shí)現(xiàn)方法為依托，根據(jù)掃描測(cè)試技術(shù)原理以及IEEE1500測(cè)試標(biāo)準(zhǔn)，綜合考慮芯核測(cè)試外殼的功能實(shí)現(xiàn)、核內(nèi)掃描鏈平衡優(yōu)化以及測(cè)試總線劃分等原則進(jìn)行SoCs并行測(cè)試單元Wrapper設(shè)計(jì)、SoCs多級(jí)測(cè)試訪問(wèn)機(jī)制TAM設(shè)計(jì)，提出了SoCs組式帶寬靈活分配TAM測(cè)試策略。在測(cè)試調(diào)度控制時(shí)，采用宏模塊控制的思想加以實(shí)現(xiàn)。將SoCs層次化測(cè)試結(jié)構(gòu)分而治之、并行測(cè)試，增加了測(cè)試的靈活性，從而提高測(cè)試效率，節(jié)約測(cè)試時(shí)間，對(duì)目前日益復(fù)雜化的層次型SoCs的可測(cè)試實(shí)現(xiàn)與優(yōu)化研究具有很大的現(xiàn)實(shí)意義。
[Abstract]:Application of integrated circuit manufacturing technology to speed the development of the embedded system chip, through the IP reuse technology of different functional modules are integrated into a chip called called system on chip, micro chip SoC. system at the same time, the scale and complexity of integrated circuit and the improvement of the IP nuclear diversity makes can implement and test the implementation of the strategy has become the difficult problem of measuring SoC chip. In recent years, in order to solve the SoC test area of excessive consumption and long test time of the problem, put forward SoCs test structure, which is nested in SoC SoC SoCs. on the one hand, SoCs test structure, and to test the package structure design the realization of the testability of the IP core, and try to reduce the number of register unit, thereby reducing the test area consumption and shorten the overall test time of SoC; on the other hand, the SoC and SoCs test to visit TAM asked the mechanism of scientific classification, rational allocation of limited TAM resources, grouping parallel test through the implementation of resource reuse strategy has become urgent to solve the problem of the SoC test. Therefore, we should test strategy for SoCs test structure is studied, which may provide reference for alleviating the cost of testing large scale integrated circuit in the future increasingly complex and expensive.
In this paper, the ITC 02 benchmark circuits SoC d695 based hierarchical structure model test SoCs system chip. Using microprogram controller, with macro command as the guide, using the hardware and software co design ideas for the design and optimization of test model, design the appropriate multi-level test access mechanism in the. The hierarchical structure with a single level test, test access mechanism of traditional SoC test implementation method as the basis, according to the principle of scanning test and IEEE1500 test standard, considering the shell core test functions, SoCs parallel test unit Wrapper design of nuclear scan chain balance optimization and test bus division principle, multistage SoCs test access mechanism of TAM design, proposed the SoCs group type flexible bandwidth allocation TAM test strategy. In the test scheduling control, using macro module control theory to realize The SoCs hierarchical test structure is divided and governed. Parallel testing increases the flexibility of testing, improves testing efficiency and saves test time. It has great practical significance for the test and optimization of SoCs, which is becoming more and more complex.

【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 喬立巖;向剛;俞洋;王帥;;基于IEEE 1500標(biāo)準(zhǔn)的IP核測(cè)試殼設(shè)計(jì)[J];電子測(cè)量技術(shù);2010年07期

2 易茂祥;梁華國(guó);陳田;;基于最佳交換遞減的芯核測(cè)試鏈平衡劃分[J];電子測(cè)量與儀器學(xué)報(bào);2009年04期

3 談恩民;王鵬;;基于NSGA-Ⅱ算法的SoC測(cè)試多目標(biāo)優(yōu)化研究[J];電子測(cè)量與儀器學(xué)報(bào);2011年03期

4 鄧立寶;喬立巖;俞洋;彭喜元;;基于差值二次分配的掃描鏈平衡算法[J];電子學(xué)報(bào);2012年02期

5 商進(jìn);張禮勇;;一種混合相容數(shù)據(jù)塊的測(cè)試數(shù)據(jù)壓縮方案[J];哈爾濱理工大學(xué)學(xué)報(bào);2011年06期

6 胡瑜,韓銀和,李華偉,呂濤,李曉維;基于雙核掃描鏈平衡的SoC測(cè)試調(diào)度[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2005年10期

7 范小鑫;李華偉;胡瑜;李曉維;;采用片內(nèi)PLL實(shí)現(xiàn)實(shí)速掃描測(cè)試的方案[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2007年03期

8 崔小樂(lè);程偉;;SoC測(cè)試訪問(wèn)機(jī)制和測(cè)試殼的蟻群聯(lián)合優(yōu)化[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2009年04期

9 張艷紅;陳朝陽(yáng);;測(cè)試基準(zhǔn)電路ITC’02剖析及其應(yīng)用現(xiàn)狀[J];計(jì)算機(jī)測(cè)量與控制;2006年07期

10 牛道恒;王紅;楊士元;成本茂;靳洋;;Re-Optimization Algorithm for SoC Wrapper-Chain Balance Using Mean-Value Approximation[J];Tsinghua Science and Technology;2007年S1期

本文編號(hào)：1394433