本文關鍵詞：超外差接收機中頻率綜合器核心電路設計　出處：《東南大學》2015年碩士論文　論文類型：學位論文

  更多相關文章： 超外差接收機 頻率綜合器 鎖相環(huán) 環(huán)形壓控振蕩器 CML分頻器 工藝角補償 NMOS開關電荷泵

【摘要】：隨著無線通信和無線控制的發(fā)展,無線控制設備已經(jīng)覆蓋到了各個領域。而國內(nèi)在此方面還未有成熟的芯片,目前已有的芯片大多來自國外大公司和國內(nèi)逆向設計公司。巨大的市場需求和國內(nèi)缺乏的技術促使形成了這一產(chǎn)業(yè)化項目。頻率綜合器一般可以分成三類：直接模擬頻率綜合器、直接數(shù)字頻率綜合器以及鎖相環(huán)頻率綜合器。由于鎖相環(huán)結(jié)構(gòu)易于片上集成,面積小,成本低,從而被目前多數(shù)移動通信芯片采用,也成為本文針對超外差結(jié)構(gòu)收發(fā)芯片采用的結(jié)構(gòu)。本文的研究內(nèi)容是超外差接收機中核心電路頻率綜合器的設計。對其中可用的各類頻率綜合器結(jié)構(gòu)進行了分析,總結(jié)了超外差接收機和各種頻率綜合器的基本工作原理,包括整數(shù)型和小數(shù)型。根據(jù)實際要求選擇了整數(shù)型頻率綜合器,對其進行了模塊和環(huán)路分析。本文研究的PLL頻率綜合器核心子模塊包括：VCO、分頻器、PFD.CP和LPF。詳細深入的闡述了其中各核心子模塊設計,從選型,輔助結(jié)構(gòu)創(chuàng)新到結(jié)構(gòu)優(yōu)化給出了完整的設計思路,并完成完整的設計、布圖流程,最終通過0.5μn CMOS工藝MPW流片,實現(xiàn)了300-450MHz寬頻率鎖定范圍,3-5.5V寬電源電壓范圍,-40～125℃寬工作溫度范圍,在帶負載全工藝角條件下提供了四路正交輸出信號幅度大于200mV,工作電流小于3mA的頻率綜合器。本文的創(chuàng)新點在于,四級差分環(huán)形振蕩器的設計中采用了工藝角檢查電路,通過獨特的二分工藝角遲滯鎖定對應補償,實現(xiàn)了寬頻率、寬電壓、寬溫度范圍的壓控特性曲線。在高速CML分頻器的設計中,增加了創(chuàng)新的自適應調(diào)節(jié)輸出點電壓和尾電流補償電路�；诨镜碾姾杀媒Y(jié)構(gòu)實現(xiàn)全NMOS開關和充電響應速度增強電路。針對產(chǎn)品級芯片設計,增加了輔助的LDO降低功耗和噪聲干擾,增加了系統(tǒng)電流鏡控制電路來調(diào)節(jié)測試,增加了過流檢查電路來降低芯片的失效風險,并同時實現(xiàn)過流自動恢復功能來保證各種惡劣環(huán)境下環(huán)路的始終鎖定,以及芯片的正常工作。頻率綜合器的發(fā)明是為了產(chǎn)生高精準的倍頻或同步時鐘,應用于具體的各種接收機、發(fā)射機、通信中的調(diào)制解調(diào)和數(shù)字集成電路中的同步時鐘產(chǎn)生等。本文涉及的315MHz和433.92MHz超外差結(jié)構(gòu)收發(fā)芯片應用在的短距離無線通信和無線控制領域,由于其頻段開放,應用前景十分廣泛,包括各類無線控制的消費類電子,安防設備,智能家居設備等。
[Abstract]:With the development of wireless communication and wireless control, wireless control devices have been covered in various fields. However, there is no mature chip in this field in China. At present, most of the existing chips come from large foreign companies and domestic reverse design companies. The huge market demand and the lack of technology at home have led to this industrialization project. Frequency synthesizers can be divided into three categories:. Direct analog frequency synthesizer. Direct digital frequency synthesizer and PLL frequency synthesizer. Because the PLL structure is easy to integrate on chip, the area is small and the cost is low, so it is adopted by most mobile communication chips. The research content of this paper is the design of the core circuit frequency synthesizer in the superheterodyne receiver. The structure of all kinds of frequency synthesizer is analyzed. . The basic working principles of the superheterodyne receiver and various frequency synthesizers, including integer type and fractional type, are summarized. The integer frequency synthesizer is selected according to the actual requirements. The core sub-modules of the PLL frequency synthesizer in this paper include: VCO, frequency divider. PFD.CP and LPF. Detailed and in-depth elaboration of each of the core sub-module design, from selection, auxiliary structure innovation to structural optimization give a complete design ideas, and complete the complete design, layout flow. Finally, 300-450 MHz wide frequency locking range and 3-5.5 V wide power supply voltage range are realized by 0.5 渭 n CMOS MPW wafer. At a wide working temperature range of -40 鈩，

本文編號：1394568