【摘要】：隨著現(xiàn)代集成電路技術(shù)的高速發(fā)展,基于電池供電的便攜式電子產(chǎn)品得到廣泛應(yīng)用,譬如iPhone、iPad、數(shù)碼相機(jī)、智能手表等消費(fèi)類電子產(chǎn)品。便攜式電子產(chǎn)品不僅在性能和功能上朝著多元化智能化發(fā)展,體積和尺寸上也越來越“小、輕、薄”。所以基于這些改變,對(duì)電源管理芯片提出了更嚴(yán)格的要求,往往要求DC-DC轉(zhuǎn)換器具有高效率、小體積、低成本等特點(diǎn)。DC-DC轉(zhuǎn)換器分為三類:低壓差線性穩(wěn)壓器(LDO)、電感型開關(guān)電源和電容型開關(guān)電源。傳統(tǒng)射頻端供電常采用線性穩(wěn)壓器,因?yàn)槠渚哂蟹�(wěn)定性好、低噪聲、使用可靠等優(yōu)點(diǎn)。所以廣泛被應(yīng)用于射頻、音頻、ADC轉(zhuǎn)換等應(yīng)用,但是其效率比較低。電感型開關(guān)電源由于采用電感線圈作為儲(chǔ)能元件,體積較大不易于片上集成且EMI較大。由于這些限制它們將難以順應(yīng)現(xiàn)代電子技術(shù)的發(fā)展潮流。電容型開關(guān)電源僅含有開關(guān)與電容元件,通過控制電容的充放電來實(shí)現(xiàn)能量的轉(zhuǎn)換,電路結(jié)構(gòu)簡(jiǎn)單,EMI較小,效率較高。同時(shí)由于電路中不存在電感元件,集成度比較高,使低成本高效率的開關(guān)電源給對(duì)噪聲敏感的射頻端供電成為可能。所以本論文對(duì)開關(guān)電容型DC-DC轉(zhuǎn)換器展開深入研究和討論,提出了一種應(yīng)用于給射頻低噪放供電的高效率低紋波的開關(guān)電容轉(zhuǎn)換器。本論文針對(duì)開關(guān)電容轉(zhuǎn)換器輸出電壓紋波較大的原因做了詳細(xì)的分析和研究,提出了梯形波驅(qū)動(dòng)的紋波抑制技術(shù)和基于飛跨電容多步充放電的電荷泵多相交織技術(shù),同時(shí)采用自適應(yīng)時(shí)鐘頻率調(diào)制,有效抑制了輸出電壓紋波。通過自適應(yīng)時(shí)鐘頻率調(diào)制,使得系統(tǒng)開關(guān)頻率隨著負(fù)載的情況線性變化,降低輸出電壓紋波的同時(shí)也提高了輕載效率�；贑SMC 0.5um CMOS工藝模型,首先用verilogA進(jìn)行系統(tǒng)模型的構(gòu)建,設(shè)計(jì)性能指標(biāo),接著對(duì)各個(gè)模塊電路進(jìn)行晶體管級(jí)設(shè)計(jì),主要包括帶隙基準(zhǔn)源、VCO、數(shù)字狀態(tài)機(jī)、開關(guān)電容陣列、ADC以及驅(qū)動(dòng)電路等。完成電路設(shè)計(jì)后對(duì)系統(tǒng)進(jìn)行spectreverilog仿真,結(jié)果顯示當(dāng)輸入電壓為5V~2.5V范圍內(nèi),最大負(fù)載電流60mA,最大輸出電壓紋波小于2mV,達(dá)到了預(yù)期設(shè)計(jì)要求。
[Abstract]:With the rapid development of modern integrated circuit technology, battery-powered portable electronic products, such as iPhone,iPad, digital camera, smartwatch and other consumer electronic products, have been widely used. Portable electronic products are not only developing towards diversified intelligence in performance and function, but also smaller, lighter and thinner in size and volume. Therefore, based on these changes, we put forward stricter requirements for power management chips, which often require that DC-DC converters have the characteristics of high efficiency, small volume and low cost. DC-DC converters can be divided into three categories: low-voltage differential linear voltage regulator (LDO),). Inductive switching power supply and capacitive switching power supply. Traditional RF terminal power supply usually uses linear voltage regulator, because it has the advantages of good stability, low noise, reliable use and so on. So it is widely used in radio frequency, audio, ADC conversion and other applications, but its efficiency is relatively low. Because inductor coil is used as energy storage element in inductive switching power supply, it is difficult to integrate on chip and EMI is larger. Because of these limitations, they will be difficult to adapt to the trend of the development of modern electronic technology. Capacitive switching power supply only contains switch and capacitor components. Energy conversion can be realized by controlling the charge and discharge of capacitance. The circuit structure is simple, EMI is small and efficiency is high. At the same time, because there is no inductor in the circuit and the integration is high, it is possible that the switching power supply with low cost and high efficiency can supply the RF terminal which is sensitive to noise. In this paper, the switched capacitive DC-DC converter is studied and discussed in depth, and a high efficiency and low ripple switching capacitor converter is proposed, which is used to supply the RF low noise amplifier with high efficiency and low ripple. In this paper, the reasons why the output voltage ripple of switched capacitor converter is large are analyzed and studied in detail, and the ripple suppression technology driven by trapezoidal wave and the charge pump multi-phase interleaving technology based on multi-step charge and discharge of flying capacitor are proposed. At the same time, adaptive clock-frequency modulation is used to suppress the output voltage ripple effectively. By adaptive clock-frequency modulation, the switching frequency of the system varies linearly with the load, reduces the output voltage ripple, and improves the efficiency of light load. Based on the CSMC 0.5um CMOS process model, the system model is constructed with verilogA, and the performance index is designed. Then the transistor level design of each module circuit is carried out, including band gap reference, VCO, digital state machine, switched capacitor array, and so on. ADC and driving circuit. When the input voltage is in the range of 5V~2.5V, the maximum load current is 60mA and the maximum output voltage ripple is less than 2mV. The simulation results show that the spectreverilog simulation results show that the system achieves the expected design requirements when the input voltage is within the range of 5V~2.5V and the maximum output voltage ripple is less than 2mV.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TM46

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本文編號(hào)：2453192