【摘要】：隨著電子系統(tǒng)的不斷進(jìn)步,電子電器設(shè)備在日常生活中占據(jù)著越來越重要的地位,同時對電網(wǎng)造成的諧波污染也日益增加,而功率因數(shù)校正(PFC)技術(shù)是提高電子設(shè)備的功率因數(shù)、減少諧波失真、降低電網(wǎng)污染、提高電能利用率的有效方法,因此,電源芯片的PFC技術(shù)成了當(dāng)前電子領(lǐng)域關(guān)注和研究的焦點之一。其中,有源功率因數(shù)校正(APFC)技術(shù)不僅能夠提高功率因數(shù)和降低總諧波失真(THD),同時因為其輸入電壓范圍大、結(jié)構(gòu)簡單、效率高等優(yōu)點而其被廣泛應(yīng)用。為了適應(yīng)低功率的電子設(shè)備應(yīng)用,本論文重點研究低成本高功率因數(shù)的PFC電源芯片的設(shè)計方法。本論文設(shè)計了一款單級Buck型功率因數(shù)校正(PFC)電源管理類芯片XD5814A,并分析其環(huán)路穩(wěn)定性。首先論文闡述了降壓型PFC電源芯片的研究背景及其技術(shù)的重要性;其次介紹了功率因數(shù)校正技術(shù)的基本定義、控制方法,并給出了電源芯片XD5814A的電氣特性指標(biāo)和系統(tǒng)功能;再次,用狀態(tài)空間平均法給Buck型拓?fù)浣Y(jié)構(gòu)建模和分析其穩(wěn)定性,并通過分析傳輸函數(shù)的零極點來提高系統(tǒng)環(huán)路的穩(wěn)定性;最后,進(jìn)行電源芯片XD5814A的關(guān)鍵子模塊和整體電路的仿真并驗證。針對以往功率因數(shù)校正電源芯片采用低帶寬濾波功能減低諧波失真而導(dǎo)致電源芯片環(huán)路系統(tǒng)的瞬態(tài)響應(yīng)慢的缺陷,本電源芯片的跨導(dǎo)運算放大器采用增強壓擺率的新穎結(jié)構(gòu);同時本電源芯片采用準(zhǔn)諧振模式的控制方式提高工作效率和采用固定導(dǎo)通時間控制實現(xiàn)交流輸入電流波形跟隨交流輸入電壓波形,從而達(dá)到高的功率因數(shù)。此外,為了提高電流控制精度,實現(xiàn)功率因數(shù)校正,本電源芯片的電感電流采樣電路獲得精確的輸出電流信息從而實現(xiàn)輸出恒流的控制;為了提高提高電源芯片的安全可靠性,在其內(nèi)部集成欠壓鎖存電路、開路保護(hù)電路和過溫保護(hù)電路等保護(hù)系統(tǒng);同時為了縮短電源芯片的研發(fā)周期,在其內(nèi)部集成了可測性電路。本論文設(shè)計的Buck型PFC電源芯片有效地減小電流畸變,很好地實現(xiàn)輸入電流跟隨輸入電壓的相位,大大降低了THD,在0.35μm,5V/40V/600V BCD工藝模型下,用Hspice工具進(jìn)行仿真與驗證,這款PFC電源芯片在輸出電壓為24V,輸出電流為0.3A(0.1Aout?I?)的情況下,功率因數(shù)(PF)等于0.977,總諧波失真(THD)等于0.21,由仿真結(jié)果可知性能良好。
[Abstract]:With the continuous progress of electronic system, electronic and electrical equipment occupies a more and more important position in daily life, at the same time, the harmonic pollution caused by power grid is also increasing day by day. Power factor correction (PFC) is an effective method to improve power factor of electronic equipment, reduce harmonic distortion, reduce power grid pollution and improve power utilization ratio. The PFC technology of power chip has become one of the focus in the field of electronics. Among them, active Power Factor Correction (APFC) technology can not only improve the power factor and reduce the total harmonic distortion (THD), but also be widely used because of its large input voltage range, simple structure, high efficiency and so on. In order to adapt to the application of low power electronic equipment, this paper focuses on the design method of low cost and high power factor PFC power chip. In this paper, a single stage Buck power factor correction (PFC) (PFC) power management chip (XD5814A,) is designed and its loop stability is analyzed. Firstly, the research background and the importance of the technology of PFC power supply chip are introduced, then the basic definition and control method of power factor correction technology are introduced, and the electrical characteristic index and system function of the power supply chip XD5814A are given. Thirdly, the state space averaging method is used to model and analyze the stability of Buck topology, and the stability of the loop is improved by analyzing the zero pole of the transmission function. Finally, the key sub-modules and the whole circuit of the power chip XD5814A are simulated and verified. In order to reduce the harmonic distortion of the power factor correction power supply chip with low bandwidth filter, the transient response of the loop system of the power supply chip is slow. The transconductance operational amplifier of the power factor correction chip adopts a novel structure of enhanced swinging rate. At the same time, the control mode of quasi-resonant mode is adopted to improve the working efficiency and the fixed on-time control is used to realize the AC input current waveform following the AC input voltage waveform, thus achieving a high power factor. In addition, in order to improve the accuracy of current control and realize power factor correction, the inductance current sampling circuit of the power supply chip obtains accurate output current information to realize the control of output constant current. In order to improve the safety and reliability of the power supply chip, the under-voltage latch circuit, open-circuit protection circuit and over-temperature protection circuit are integrated into the power chip. In order to shorten the research and development cycle of the power chip, the testability circuit is integrated inside the chip. The Buck type PFC power supply chip designed in this paper can effectively reduce the current distortion, realize the phase of input current following the input voltage, and greatly reduce the THD, process model under 0.35 渭 m / 5 V / 40 V / 600V BCD process model. The PFC power supply chip is simulated and verified by Hspice tool. The output voltage is 24V and the output current is 0.3A (0.1Aouti?) When the power factor (PF) is 0.977 and the total harmonic distortion (THD) is 0.21, the simulation results show that the performance is good.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM46

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 胡慶波;瞿博;呂征宇;;一種新穎的應(yīng)用于PFC電路中電流控制的方法[J];中國電機工程學(xué)報;2006年03期

，

本文編號：2362160