雙通道數(shù)字化儀中頻及基帶信號處理模塊的設(shè)計與實現(xiàn)
發(fā)布時間：2018-09-01 11:39
【摘要】：數(shù)字化儀是模擬信號與數(shù)字信號對接的重要手段,并同時具有數(shù)字信號處理能力。具備雙通道高速信號采集和處理功能的數(shù)字化儀通過與接收機模塊和工控機模塊的互聯(lián),可以完成示波器、頻譜分析儀、無線通信分析儀、無線電測向儀等系統(tǒng)。高速的雙通道數(shù)字化儀可以同時對兩個模擬目標進行分析,在實時頻譜分析儀中即可以完成所覆蓋頻率范圍內(nèi)任意兩個頻點的實時分析,也可以分別對基帶信號的I、Q兩路同步采集完成基帶I/Q調(diào)制分析;在無線電測向系統(tǒng)中可以一路采集參考通道,另一路輪流采集各接收通道,完成測向定位的功能。本文主要基于PXI總線雙通道數(shù)字化儀項目運用背景,提出了PXI總線雙通道數(shù)字化儀的設(shè)計方案,重點對雙通道數(shù)字化儀中頻及基帶信號處理模塊關(guān)鍵技術(shù)進行了大量研究并實現(xiàn)了具體電路。其中雙路ADC與FPGA之間交互數(shù)據(jù)位寬和時鐘頻率都很高(采用DDR傳輸模式),為了保證每次完成布局布線數(shù)據(jù)與時鐘(DCO)不因在FPGA內(nèi)部產(chǎn)生相對延遲而造成讀數(shù)錯誤,本文設(shè)計并實現(xiàn)了一種能完成數(shù)據(jù)時鐘自動同步的DLL電路,提高了開發(fā)效率;而多檔位數(shù)字下變頻單元提出了一種高效的分數(shù)倍抽取濾波器組架構(gòu)(CIC抽取+CIC補償+CIC插值),核心的分數(shù)倍抽取濾波電路都采用高效結(jié)構(gòu)實現(xiàn),節(jié)省資源的同時使得雙通道數(shù)字化儀的RTBW(實時分辨率帶寬)達到了42個,從而滿足了更靈活的分析需求;針對為了節(jié)省或高效利用片內(nèi)資源而減小處理位寬所引起的動態(tài)范圍損失的問題,本文提出了一種動態(tài)范圍補償?shù)母咝г鲆婵刂齐娐方Y(jié)構(gòu),并避免了除法運算操作,在減小位寬和資源消耗的同時也保證了動態(tài)范圍;為了滿足用戶對I/Q基帶信號調(diào)制分析的需求,本文充分利用雙通道數(shù)字化儀可以完成雙路信號并行采集的特點,提出了一種能對0~51.2Msps范圍內(nèi)任意碼率的QPSK和4~256QAM基帶信號完成調(diào)制分析的硬件處理架構(gòu)。本論文所論述的雙通道數(shù)字化儀中頻及基帶信號處理模塊各個功能單元能夠正�？煽抗ぷ�,達到預(yù)定指標和工程運用要求,在大量實踐與測試中性能穩(wěn)定,該數(shù)字化儀可運用于常見的通信測試系統(tǒng)或儀器。
[Abstract]:Digitizer is an important means of docking analog signal and digital signal, and has the ability of digital signal processing at the same time. The digital instrument with dual channel high-speed signal acquisition and processing can complete the oscilloscope, spectrum analyzer, wireless communication analyzer, radio direction finder and so on through the interconnection with receiver module and industrial computer module. High-speed dual-channel digitizer can analyze two analog targets at the same time. In the real-time spectrum analyzer, the real-time analysis of any two frequency points in the frequency range can be completed. In the radio direction-finding system, reference channels can be collected one way, and the receiving channels can be collected in turn on the other side to complete the function of direction finding and positioning. Based on the application background of PXI bus dual-channel digitizer, this paper puts forward the design scheme of PXI bus dual-channel digitizer. The key technology of if and baseband signal processing module of dual channel digitizer is studied and the specific circuit is realized. The interactive data bit width and clock frequency between dual ADC and FPGA are both very high (using DDR transmission mode). In order to ensure that each completion of layout routing data and clock (DCO) does not cause reading errors due to the relative delay within FPGA. In this paper, we design and implement a kind of DLL circuit which can realize the automatic synchronization of data clock, and improve the efficiency of development. A high efficient fractional decimation filter bank architecture (CIC decimation CIC compensated CIC interpolation) is proposed by multi-shift digital down-conversion unit. The core fractional decimation filter circuits are all implemented with efficient structure. At the same time, the RTBW (real-time resolution bandwidth) of the dual-channel digitizer is 42, which meets the more flexible analysis requirements. In order to reduce the dynamic range loss caused by processing bit width in order to save or efficiently utilize in-chip resources, this paper presents an efficient gain control circuit structure with dynamic range compensation, and avoids division operation. In order to meet the needs of the user for I / Q baseband signal modulation analysis, this paper makes full use of the dual channel digitizer to complete the dual signal parallel acquisition. This paper presents a hardware processing architecture that can modulate and analyze QPSK and 4~256QAM baseband signals at any bit rate in the 0~51.2Msps range. In this paper, if and baseband signal processing modules of the dual-channel digitizer can work normally and reliably, which can meet the requirements of predefined targets and engineering applications, and have a stable performance in a large number of practices and tests. The digitizer can be used in common communication test systems or instruments.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM935
本文編號：2217087
[Abstract]:Digitizer is an important means of docking analog signal and digital signal, and has the ability of digital signal processing at the same time. The digital instrument with dual channel high-speed signal acquisition and processing can complete the oscilloscope, spectrum analyzer, wireless communication analyzer, radio direction finder and so on through the interconnection with receiver module and industrial computer module. High-speed dual-channel digitizer can analyze two analog targets at the same time. In the real-time spectrum analyzer, the real-time analysis of any two frequency points in the frequency range can be completed. In the radio direction-finding system, reference channels can be collected one way, and the receiving channels can be collected in turn on the other side to complete the function of direction finding and positioning. Based on the application background of PXI bus dual-channel digitizer, this paper puts forward the design scheme of PXI bus dual-channel digitizer. The key technology of if and baseband signal processing module of dual channel digitizer is studied and the specific circuit is realized. The interactive data bit width and clock frequency between dual ADC and FPGA are both very high (using DDR transmission mode). In order to ensure that each completion of layout routing data and clock (DCO) does not cause reading errors due to the relative delay within FPGA. In this paper, we design and implement a kind of DLL circuit which can realize the automatic synchronization of data clock, and improve the efficiency of development. A high efficient fractional decimation filter bank architecture (CIC decimation CIC compensated CIC interpolation) is proposed by multi-shift digital down-conversion unit. The core fractional decimation filter circuits are all implemented with efficient structure. At the same time, the RTBW (real-time resolution bandwidth) of the dual-channel digitizer is 42, which meets the more flexible analysis requirements. In order to reduce the dynamic range loss caused by processing bit width in order to save or efficiently utilize in-chip resources, this paper presents an efficient gain control circuit structure with dynamic range compensation, and avoids division operation. In order to meet the needs of the user for I / Q baseband signal modulation analysis, this paper makes full use of the dual channel digitizer to complete the dual signal parallel acquisition. This paper presents a hardware processing architecture that can modulate and analyze QPSK and 4~256QAM baseband signals at any bit rate in the 0~51.2Msps range. In this paper, if and baseband signal processing modules of the dual-channel digitizer can work normally and reliably, which can meet the requirements of predefined targets and engineering applications, and have a stable performance in a large number of practices and tests. The digitizer can be used in common communication test systems or instruments.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM935
【參考文獻】
相關(guān)碩士學(xué)位論文 前1條
1 宋丹;數(shù)字下變頻器中自動增益控制電路的設(shè)計與實現(xiàn)[D];電子科技大學(xué);2006年
，本文編號：2217087
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