AIS信號接收解調(diào)算法研究與實(shí)現(xiàn)
發(fā)布時間：2019-03-19 19:53
【摘要】：船舶自動識別系統(tǒng)(Automatic Identify System,簡稱AIS)是一種操作在海上甚高頻(Very High Frequency,簡稱VHF)頻帶的自動連續(xù)廣播系統(tǒng),用于實(shí)現(xiàn)船舶與船舶間、船舶與基站間的相互通信。為了擴(kuò)大AIS的覆蓋范圍,星載AIS應(yīng)運(yùn)而生,它為全球所有裝有AIS設(shè)備的海上移動裝置提供基本的監(jiān)測信息。然而星載AIS也帶來了多普勒頻偏和多信號碰撞的問題。因此研究星載條件下AIS信號的接收解調(diào)技術(shù)具有重要的理論意義和應(yīng)用價值。本文根據(jù)AIS信號處理系統(tǒng)的實(shí)際需求,確定了基于TI公司低功耗浮點(diǎn)處理器TMS320C6748和Xilinx公司Artix-7系列FPGA的硬件平臺。在對AIS信號解調(diào)算法及其分離技術(shù)進(jìn)行了大量仿真研究的同時,在該平臺上實(shí)現(xiàn)了AIS信號解調(diào)算法。本文主要研究內(nèi)容有：重點(diǎn)研究了AIS信號的非相干解調(diào)算法。分別討論了幀頭檢測、頻偏估計及符號定時技術(shù),并給出了不同測頻和定時方法的比較。同時就頻偏和定時對信號解調(diào)性能的影響進(jìn)行了大量的仿真分析。提出了星載條件下的多信號分離算法。星載AIS由于覆蓋范圍大而易引起多信號碰撞,當(dāng)兩路AIS信號幅度差異較大時,可以先解調(diào)幅度較大的信號,然后根據(jù)解調(diào)得到的符號序列以及幅度、相位和時延等參數(shù)估計值重構(gòu)出幅度較大的信號,從而實(shí)現(xiàn)同信道干擾下AIS信號分離。實(shí)現(xiàn)了基于Xilinx Artix-7平臺的信號幀頭檢測模塊和基于TI TMS320C6748平臺的AIS基帶信號解調(diào)模塊。對于每一模塊的具體實(shí)現(xiàn)方法給出了詳細(xì)說明。深入分析了實(shí)現(xiàn)過程中遇到的問題并給出實(shí)際解決方案。實(shí)現(xiàn)了FPGA與DSP之間的EMIF通信,DSP與PC的UART通信,并對整個系統(tǒng)進(jìn)行了功能和性能的測試,測試結(jié)果都滿足實(shí)際需求。
[Abstract]:Ship automatic Identification system (Automatic Identify System,) is an automatic continuous broadcast system which operates the VHF (Very High Frequency, (VHF) band at sea. It is used to realize the communication between ship and base station. In order to expand the coverage of AIS, Spaceborne AIS emerged as the times require. It provides basic monitoring information for all marine mobile devices equipped with AIS equipment in the world. However, spaceborne AIS also brings the problems of Doppler frequency offset and multi-signal collision. Therefore, it is of great theoretical significance and application value to study the receiving and demodulating technology of AIS signal under spaceborne conditions. According to the actual requirement of AIS signal processing system, the hardware platform based on low-power floating-point processor TMS320C6748 of TI company and Artix-7 series FPGA of Xilinx company is determined in this paper. Based on the simulation of AIS signal demodulation algorithm and its separation technology, the AIS signal demodulation algorithm is implemented on this platform. The main contents of this paper are as follows: the non-coherent demodulation algorithm of AIS signal is studied in detail. The frame head detection, frequency offset estimation and symbol timing techniques are discussed respectively, and the comparison of different frequency measurement and timing methods is given. At the same time, the effect of frequency offset and timing on signal demodulation performance is simulated and analyzed. A multi-signal separation algorithm under spaceborne conditions is proposed. Spaceborne AIS is easy to cause multi-signal collision because of its wide coverage. When the amplitude difference between two AIS signals is large, the signals with larger amplitude can be demodulated first, and then according to the demodulated symbol sequence and amplitude, The parameters such as phase and time delay are used to reconstruct the signals with larger amplitude, so that the AIS signals can be separated under co-channel interference. The frame header detection module based on Xilinx Artix-7 platform and the AIS baseband signal demodulation module based on TI TMS320C6748 platform are implemented. The detailed implementation method of each module is given in this paper. In-depth analysis of the problems encountered in the process of implementation and practical solutions are given. The EMIF communication between FPGA and DSP and the UART communication between DSP and PC are realized. The function and performance of the whole system are tested, and the test results meet the actual requirements.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：U675.7
[Abstract]:Ship automatic Identification system (Automatic Identify System,) is an automatic continuous broadcast system which operates the VHF (Very High Frequency, (VHF) band at sea. It is used to realize the communication between ship and base station. In order to expand the coverage of AIS, Spaceborne AIS emerged as the times require. It provides basic monitoring information for all marine mobile devices equipped with AIS equipment in the world. However, spaceborne AIS also brings the problems of Doppler frequency offset and multi-signal collision. Therefore, it is of great theoretical significance and application value to study the receiving and demodulating technology of AIS signal under spaceborne conditions. According to the actual requirement of AIS signal processing system, the hardware platform based on low-power floating-point processor TMS320C6748 of TI company and Artix-7 series FPGA of Xilinx company is determined in this paper. Based on the simulation of AIS signal demodulation algorithm and its separation technology, the AIS signal demodulation algorithm is implemented on this platform. The main contents of this paper are as follows: the non-coherent demodulation algorithm of AIS signal is studied in detail. The frame head detection, frequency offset estimation and symbol timing techniques are discussed respectively, and the comparison of different frequency measurement and timing methods is given. At the same time, the effect of frequency offset and timing on signal demodulation performance is simulated and analyzed. A multi-signal separation algorithm under spaceborne conditions is proposed. Spaceborne AIS is easy to cause multi-signal collision because of its wide coverage. When the amplitude difference between two AIS signals is large, the signals with larger amplitude can be demodulated first, and then according to the demodulated symbol sequence and amplitude, The parameters such as phase and time delay are used to reconstruct the signals with larger amplitude, so that the AIS signals can be separated under co-channel interference. The frame header detection module based on Xilinx Artix-7 platform and the AIS baseband signal demodulation module based on TI TMS320C6748 platform are implemented. The detailed implementation method of each module is given in this paper. In-depth analysis of the problems encountered in the process of implementation and practical solutions are given. The EMIF communication between FPGA and DSP and the UART communication between DSP and PC are realized. The function and performance of the whole system are tested, and the test results meet the actual requirements.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：U675.7
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