基于FPGA的AES和RSA混合加密系統(tǒng)設(shè)計(jì)實(shí)現(xiàn)
[Abstract]:At present, the world has entered the information age, computer network has been rapid development, it is related to all aspects of social life. Enjoying the network brings us convenience, but also faces many problems, one of the most prominent problems is the problem of information security. All kinds of confidential information, such as national security, political, economic and corporate confidential and private information, so the problem of information security is particularly prominent. Therefore, many countries in this field of information security research work. Information security technology, especially encryption technology, is the key infrastructure related to the country. It is best not to use other people's technology in the core part, so the research of information security and cryptography is very important. In our country, the research and practice of information security started relatively late, compared with developed countries, there is still a big gap, and the problem of information security is more prominent. Firstly, this paper introduces the knowledge of cryptography, and introduces two encryption algorithms, AES and RSA, as well as their mathematical basis, overall structure and different implementation methods. This paper analyzes the implementation of Sbox in AES algorithm, finally determines the way of using look-up table to store, and puts forward an improved scheme to solve the problem that the operation speed of RSA algorithm is too slow, and implements the improved algorithm by hardware, compares and selects their respective implementation methods, and determines the implementation mode which is convenient for FPGA implementation. This paper analyzes the advantages and disadvantages of symmetric cryptography and asymmetric cryptography, and determines that AES and RSA encryption algorithms are used to realize encryption algorithm, RSA encryption and decryption module realizes digital signature and decryption, and AES encryption key. AES encryption module is the core part, which mainly completes the encryption function of data. Each module is programmed with Verilog VHDL language and the function simulation is carried out. The ISE software of Xinlix company is selected, and the simulation results of FPGA show that the scheme accords with the actual encryption requirements. The Modelsim simulation software of Mentor company is used to verify that the Virtex6-XC6VLX240T, of Xilinx company is selected as the correct function and meets the design requirements. Finally, the paper is summarized and discussed. The innovation of this paper is mainly reflected in: using hybrid encryption to make the encryption system more secure; aiming at the problem that the speed of RSA algorithm is too slow, an improved Montgomery algorithm is proposed, which makes the operation of RSA faster and convenient for hardware implementation.
【學(xué)位授予單位】:北方工業(yè)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2014
【分類號(hào)】:TN918.4
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