基于以太網(wǎng)的音頻遠(yuǎn)程監(jiān)控系統(tǒng)設(shè)計
發(fā)布時間：2019-02-19 14:51
【摘要】：隨著信息技術(shù)以及網(wǎng)絡(luò)技術(shù)的飛速發(fā)展，因特網(wǎng)在音頻視頻、智能交通、工業(yè)控制以及航天測控領(lǐng)域已經(jīng)有了越來越廣泛的應(yīng)用。本文基于嵌入式系統(tǒng)設(shè)計，以FPGA為核心設(shè)計了一種音頻遠(yuǎn)程監(jiān)控系統(tǒng)，實現(xiàn)了音頻數(shù)據(jù)的前端處理，包括模數(shù)轉(zhuǎn)換以及音頻數(shù)據(jù)壓縮編碼的動作，同時在FPGA完成了因特網(wǎng)TCP/IP協(xié)議以及MAC控制器的設(shè)計與實現(xiàn)，最終將依據(jù)TCP/IP協(xié)議的規(guī)范打包完成的音頻數(shù)據(jù)包通過互聯(lián)網(wǎng)傳送至相應(yīng)的監(jiān)控平臺。 本系統(tǒng)設(shè)計中，采用了ADPCM編碼算法實現(xiàn)了在FPGA內(nèi)音頻數(shù)據(jù)的壓縮編碼過程。自適應(yīng)差分脈沖編碼調(diào)制（ADPCM）采用自適應(yīng)量化方法和自適應(yīng)預(yù)測方法，對PCM(脈沖編碼調(diào)制)語音信號進(jìn)行再壓縮，，實現(xiàn)了一種有效的語音信號波形編碼壓縮方案。 傳統(tǒng)的基于CPU軟件實現(xiàn)TCP/IP協(xié)議的處理方式，無論是在處理速度，還是穩(wěn)定性方面，都無法與基于硬件的實現(xiàn)相比，而且基于軟件的實現(xiàn)會占用大量的CPU資源、浪費存儲空間。當(dāng)網(wǎng)絡(luò)通信的速度達(dá)到吉比特數(shù)量級時，這種基于CPU軟件實現(xiàn)TCP/IP協(xié)議的處理方式就很難完成要求。其成本與穩(wěn)定性將會大大的制約這種處理方式。通過硬件邏輯實現(xiàn)的TCP/IP協(xié)議，能夠大大提高數(shù)據(jù)的傳輸處理能力。而FPGA(Field Programmable Gate Array，即現(xiàn)場可編程門陣列)內(nèi)部具有豐富的可編程邏輯資源，通過硬件描述語言Verilog或VHDL，能夠在FPGA中實現(xiàn)各種復(fù)雜的硬件邏輯。通過FPGA實現(xiàn)的TCP/IP協(xié)議模塊，由于它是功能專用的硬件模塊，其處理速度非常高，數(shù)據(jù)通信速度能達(dá)到10G以上，這是傳統(tǒng)的基于CPU軟件實現(xiàn)方案所很難達(dá)到的。 現(xiàn)在，F(xiàn)PGA開發(fā)工具種類繁多、智能化高、功能強大，應(yīng)用各種工具可以完成從輸入、綜合、實現(xiàn)到配置芯片等一系列功能。而且還有很多工具可以完成對設(shè)計的仿真、優(yōu)化、約束、在線調(diào)試等功能，這使FPGA的開發(fā)周期比較短，產(chǎn)品上市時間快。而且隨著FPGA的不斷發(fā)展，其規(guī)模不斷加大，成本不斷降低，并且還能將各種功能模塊做成具有知識產(chǎn)權(quán)的IP核，這樣非常方便功能模塊的移植。
[Abstract]:With the rapid development of information technology and network technology, the Internet has been more and more widely used in the fields of audio and video, intelligent transportation, industrial control and aerospace measurement and control. Based on the embedded system design, this paper designs an audio remote monitoring system with FPGA as the core, which realizes the front-end processing of audio data, including the action of analog-to-digital conversion and audio data compression and coding. At the same time, the design and implementation of the Internet TCP/IP protocol and the MAC controller are completed in FPGA. Finally, the audio packets packaged according to the standard of TCP/IP protocol are transmitted to the corresponding monitoring platform via the Internet. In the design of this system, ADPCM coding algorithm is used to realize the compression and coding process of audio data in FPGA. Adaptive differential pulse coding modulation (ADPCM) uses adaptive quantization method and adaptive prediction method to recompress the speech signal of PCM (Pulse coded Modulation) and realize an effective scheme of waveform coding compression of speech signal. The traditional TCP/IP protocol based on CPU software can not be compared with the hardware implementation in terms of processing speed and stability, and the implementation based on software will consume a lot of CPU resources. Waste storage space. When the speed of network communication reaches the order of gigabit, it is difficult to implement the TCP/IP protocol based on CPU software. Its cost and stability will greatly constrain this approach. The TCP/IP protocol realized by hardware logic can greatly improve the ability of data transmission and processing. FPGA (Field Programmable Gate Array, (Field Programmable Gate Array) has abundant programmable logic resources, and it can realize various complex hardware logic in FPGA by hardware description language Verilog or VHDL,. The TCP/IP protocol module realized by FPGA, because it is a special hardware module, its processing speed is very high, and the data communication speed can reach more than 10G, which is very difficult to achieve by the traditional software implementation scheme based on CPU. At present, FPGA development tools are various, intelligent and powerful. The application of various tools can complete a series of functions from input, synthesis, realization to configuration chip. There are also many tools to complete the design of simulation, optimization, constraints, on-line debugging and other functions, which makes the FPGA development cycle is relatively short, product launch time is fast. With the continuous development of FPGA, its scale is increasing, the cost is decreasing, and all kinds of functional modules can be made into IP cores with intellectual property rights, which is very convenient for the transplantation of functional modules.
【學(xué)位授予單位】：成都理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TN912.3;TN791
[Abstract]:With the rapid development of information technology and network technology, the Internet has been more and more widely used in the fields of audio and video, intelligent transportation, industrial control and aerospace measurement and control. Based on the embedded system design, this paper designs an audio remote monitoring system with FPGA as the core, which realizes the front-end processing of audio data, including the action of analog-to-digital conversion and audio data compression and coding. At the same time, the design and implementation of the Internet TCP/IP protocol and the MAC controller are completed in FPGA. Finally, the audio packets packaged according to the standard of TCP/IP protocol are transmitted to the corresponding monitoring platform via the Internet. In the design of this system, ADPCM coding algorithm is used to realize the compression and coding process of audio data in FPGA. Adaptive differential pulse coding modulation (ADPCM) uses adaptive quantization method and adaptive prediction method to recompress the speech signal of PCM (Pulse coded Modulation) and realize an effective scheme of waveform coding compression of speech signal. The traditional TCP/IP protocol based on CPU software can not be compared with the hardware implementation in terms of processing speed and stability, and the implementation based on software will consume a lot of CPU resources. Waste storage space. When the speed of network communication reaches the order of gigabit, it is difficult to implement the TCP/IP protocol based on CPU software. Its cost and stability will greatly constrain this approach. The TCP/IP protocol realized by hardware logic can greatly improve the ability of data transmission and processing. FPGA (Field Programmable Gate Array, (Field Programmable Gate Array) has abundant programmable logic resources, and it can realize various complex hardware logic in FPGA by hardware description language Verilog or VHDL,. The TCP/IP protocol module realized by FPGA, because it is a special hardware module, its processing speed is very high, and the data communication speed can reach more than 10G, which is very difficult to achieve by the traditional software implementation scheme based on CPU. At present, FPGA development tools are various, intelligent and powerful. The application of various tools can complete a series of functions from input, synthesis, realization to configuration chip. There are also many tools to complete the design of simulation, optimization, constraints, on-line debugging and other functions, which makes the FPGA development cycle is relatively short, product launch time is fast. With the continuous development of FPGA, its scale is increasing, the cost is decreasing, and all kinds of functional modules can be made into IP cores with intellectual property rights, which is very convenient for the transplantation of functional modules.
【學(xué)位授予單位】：成都理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TN912.3;TN791
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 張s
本文編號：2426607
本文鏈接：http://sikaile.net/falvlunwen/zhishichanquanfa/2426607.html
最近更新
教材專著
