保護(hù)大規(guī)模集成電路知識產(chǎn)權(quán)的動態(tài)水印技術(shù)研究
發(fā)布時間：2018-11-15 11:39
【摘要】：隨著半導(dǎo)體工藝的飛速發(fā)展，集成電路設(shè)計進(jìn)入了片上系統(tǒng)（SOC: system-on-a-chip）時代。使用可復(fù)用的IP核（IP: intellectual property）技術(shù)是SOC的主流設(shè)計方法學(xué)�？蓮�(fù)用IP核技術(shù)促進(jìn)了IP核的交易，但是同時使IP核盜版、濫用等侵權(quán)現(xiàn)象大肆猖獗。為了保護(hù)IP核設(shè)計者和合法使用者的利益，學(xué)者提出許多保護(hù)IP核的水印技術(shù)，使得IP核水印技術(shù)受到越來越多的關(guān)注。 根據(jù)水印技術(shù)檢測機(jī)制的不同，水印技術(shù)可以分為靜態(tài)水印技術(shù)和動態(tài)水印技術(shù)，動態(tài)水印技術(shù)由于其易于檢測的優(yōu)點(diǎn)成為水印技術(shù)研究熱點(diǎn)，然而動態(tài)水印技術(shù)仍然面臨著水印技術(shù)的開銷大，，魯棒性差的問題。針對動態(tài)水印存在的問題，本課題主要研究FSM（finite-state machine）和DFT（design-for-testability）動態(tài)水印技術(shù)，具體包括以下內(nèi)容： 本課題提出一種基于狀態(tài)的FSM水印方案。水印信息被嵌入到一個特定的狀態(tài)序列中，當(dāng)施加一個特定的輸入序列與含水印的STG，STG經(jīng)歷一個狀態(tài)序列，根據(jù)狀態(tài)的奇偶性，每個狀態(tài)對應(yīng)的值匹配水印信息，最后通過確定狀態(tài)轉(zhuǎn)移上的輸出值降低水印開銷。實驗結(jié)果表明此方案具有較高的魯棒性和產(chǎn)權(quán)可靠性，但是由于在水印嵌入過程中新加的轉(zhuǎn)移數(shù)目比較多，導(dǎo)致水印開銷比較大。為了減少新加轉(zhuǎn)移的數(shù)目降低水印開銷，本課題對該方案作了進(jìn)一步的改進(jìn)。 本課題提出一種基于BIST測試響應(yīng)壓縮優(yōu)化算法的DFT水印技術(shù)，在實現(xiàn)原始優(yōu)化算法的過程中發(fā)現(xiàn)了原算法的不足，于是本課題提出了一種改進(jìn)的測試響應(yīng)壓縮器設(shè)計方法，在改進(jìn)的算法中，對于一個固定的測試向量集，首先收集針對每一個故障的所有測試響應(yīng)。在壓縮的過程中，如果某一故障由于添加一個門被淹沒了，就搜尋這一故障其余的測試響應(yīng)不重新執(zhí)行ATPG。當(dāng)在響應(yīng)壓縮器設(shè)計過程中，添加一個基本門不得不引入冗余時，開始使用XOR門去結(jié)合輸出端。實驗結(jié)果表明對于比較大的電路，改進(jìn)的算法和原始算法在面積開銷相同的情況下，可以達(dá)到近視相同的壓縮率，但是改進(jìn)的算法不需要使用ATPG。本課題在上述改進(jìn)的優(yōu)化算法的基礎(chǔ)上實現(xiàn)了一種DFT水印技術(shù)，在該水印方案中，首先選定特定輸出端，當(dāng)選擇門結(jié)合特定的輸出端時，在一個特定的輸入下，使所選門的輸出值恰好和水印信息匹配。分析顯示該方案具有較高魯棒性和產(chǎn)權(quán)可靠性，實驗結(jié)果表明該水印技術(shù)對原始壓縮電路的壓縮率和面積影響都比較小。 為了解決動態(tài)水印技術(shù)存在的問題，本課題提出了一種新的FSM和DFT水印技術(shù)。FSM水印技術(shù)魯棒性較高但是水印開銷比較大，DFT水印技術(shù)具有高魯棒性，低開銷的特點(diǎn)，本課題實現(xiàn)了預(yù)期的目標(biāo)。
[Abstract]:With the rapid development of semiconductor technology, integrated circuit design has entered the era of SOC: system-on-a-chip. Using reusable IP core (IP: intellectual property) technology is the mainstream design methodology of SOC. Reusable IP technology promotes the trade of IP nuclear, but it also makes piracy and abuse of IP nuclear rampant. In order to protect the interests of the designers and legitimate users of the IP core, many watermarking techniques are proposed to protect the IP core, which makes the IP core watermarking technology receive more and more attention. According to the different detection mechanism of watermarking technology, watermarking technology can be divided into static watermarking technology and dynamic watermarking technology. Dynamic watermarking technology has become a hot research topic because of its advantages of easy detection. However, dynamic watermarking still faces the problem of high cost and poor robustness. Aiming at the problems of dynamic watermarking, this paper mainly studies FSM (finite-state machine) and DFT (design-for-testability) dynamic watermarking technology, including the following contents: this paper proposes a state-based FSM watermarking scheme. The watermark information is embedded in a specific state sequence. When a specific input sequence is applied to the watermark, the watermark information is matched by the corresponding value of each state according to the parity of the state. Finally, the watermark overhead is reduced by determining the output value of the state transition. The experimental results show that this scheme has high robustness and property right reliability, but due to the large number of new transfers added in the process of watermark embedding, the watermark cost is relatively large. In order to reduce the number of new transfers and reduce the watermark overhead, the scheme is further improved. In this paper, a DFT watermarking technique based on BIST test response compression optimization algorithm is proposed. In the process of realizing the original optimization algorithm, the shortcomings of the original algorithm are found, so an improved design method of the test response compressor is proposed. In the improved algorithm, for a fixed set of test vectors, all the test responses for each fault are first collected. During compression, if a fault is flooded by adding a gate, search for the fault and the rest of the test response does not re-execute ATPG. When a basic gate has to be introduced redundancy in the design of the response compressor, the XOR gate is used to combine the output. Experimental results show that for larger circuits, the improved algorithm and the original algorithm can achieve the same compression ratio of myopia under the same area cost, but the improved algorithm does not need to use ATPG.. In this paper, a DFT watermarking technique is implemented on the basis of the above improved optimization algorithm. In this scheme, a specific output is first selected, and when the gate is combined with a specific output, under a specific input, The output value of the selected gate matches the watermark information. The analysis shows that the scheme has high robustness and property right reliability. The experimental results show that the watermark technology has little effect on the compression ratio and area of the original compression circuit. In order to solve the problem of dynamic watermarking technology, this paper proposes a new FSM and DFT watermarking technology. FSM watermarking technology has high robustness but high watermark overhead, and DFT watermarking technology has the characteristics of high robustness and low cost. This subject has achieved the expected goal.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP309.7
本文編號：2333205
[Abstract]:With the rapid development of semiconductor technology, integrated circuit design has entered the era of SOC: system-on-a-chip. Using reusable IP core (IP: intellectual property) technology is the mainstream design methodology of SOC. Reusable IP technology promotes the trade of IP nuclear, but it also makes piracy and abuse of IP nuclear rampant. In order to protect the interests of the designers and legitimate users of the IP core, many watermarking techniques are proposed to protect the IP core, which makes the IP core watermarking technology receive more and more attention. According to the different detection mechanism of watermarking technology, watermarking technology can be divided into static watermarking technology and dynamic watermarking technology. Dynamic watermarking technology has become a hot research topic because of its advantages of easy detection. However, dynamic watermarking still faces the problem of high cost and poor robustness. Aiming at the problems of dynamic watermarking, this paper mainly studies FSM (finite-state machine) and DFT (design-for-testability) dynamic watermarking technology, including the following contents: this paper proposes a state-based FSM watermarking scheme. The watermark information is embedded in a specific state sequence. When a specific input sequence is applied to the watermark, the watermark information is matched by the corresponding value of each state according to the parity of the state. Finally, the watermark overhead is reduced by determining the output value of the state transition. The experimental results show that this scheme has high robustness and property right reliability, but due to the large number of new transfers added in the process of watermark embedding, the watermark cost is relatively large. In order to reduce the number of new transfers and reduce the watermark overhead, the scheme is further improved. In this paper, a DFT watermarking technique based on BIST test response compression optimization algorithm is proposed. In the process of realizing the original optimization algorithm, the shortcomings of the original algorithm are found, so an improved design method of the test response compressor is proposed. In the improved algorithm, for a fixed set of test vectors, all the test responses for each fault are first collected. During compression, if a fault is flooded by adding a gate, search for the fault and the rest of the test response does not re-execute ATPG. When a basic gate has to be introduced redundancy in the design of the response compressor, the XOR gate is used to combine the output. Experimental results show that for larger circuits, the improved algorithm and the original algorithm can achieve the same compression ratio of myopia under the same area cost, but the improved algorithm does not need to use ATPG.. In this paper, a DFT watermarking technique is implemented on the basis of the above improved optimization algorithm. In this scheme, a specific output is first selected, and when the gate is combined with a specific output, under a specific input, The output value of the selected gate matches the watermark information. The analysis shows that the scheme has high robustness and property right reliability. The experimental results show that the watermark technology has little effect on the compression ratio and area of the original compression circuit. In order to solve the problem of dynamic watermarking technology, this paper proposes a new FSM and DFT watermarking technology. FSM watermarking technology has high robustness but high watermark overhead, and DFT watermarking technology has the characteristics of high robustness and low cost. This subject has achieved the expected goal.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP309.7
本文編號：2333205
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