多位∑-Δ模數(shù)轉(zhuǎn)換技術(shù)研究
發(fā)布時間：2018-10-13 12:08
【摘要】：Σ-Δ模數(shù)轉(zhuǎn)換器因其線性度好、精度高、功耗低等優(yōu)點而被廣泛應(yīng)用在視頻、多媒體、地震勘測儀器、聲納、電子測量和中等分辨率的系統(tǒng)中。目前，多位量化的高精度Σ-Δ模數(shù)轉(zhuǎn)換技術(shù)是人們研究的熱點，而國內(nèi)在模數(shù)轉(zhuǎn)換器方面的研究還處于開始起步階段。對Σ-Δ模數(shù)轉(zhuǎn)換器體系結(jié)構(gòu)的研究和設(shè)計水平與國外的先進水平相比存在很大差距，需要我們加強在Σ-Δ模數(shù)轉(zhuǎn)換技術(shù)上的研發(fā)力度，研究擁有自主知識產(chǎn)權(quán)的Σ-Δ模數(shù)轉(zhuǎn)換器。因此，對多位Σ-Δ模數(shù)轉(zhuǎn)換技術(shù)的研究無論在學(xué)術(shù)上還是經(jīng)濟上都有著非常重要的意義。 本文詳細闡述了Σ-Δ型轉(zhuǎn)換器的基本原理、結(jié)構(gòu)以及多位量化Σ-Δ模數(shù)轉(zhuǎn)換器設(shè)計的關(guān)鍵技術(shù)。在研究Σ-Δ型模數(shù)轉(zhuǎn)換器各種結(jié)構(gòu)的基礎(chǔ)上，重點研究了多位量化結(jié)構(gòu)，討論了多位量化器位數(shù)與Σ-Δ模數(shù)轉(zhuǎn)換器精度的關(guān)系。并利用多位量化Σ-Δ模數(shù)轉(zhuǎn)換技術(shù)設(shè)計了24位多位量化Σ-Δ模數(shù)轉(zhuǎn)換器。 在系統(tǒng)級設(shè)計過程中，，首先是Σ-Δ調(diào)制器的系統(tǒng)設(shè)計，根據(jù)Σ-Δ調(diào)制器的相關(guān)知識，確定了Σ-Δ調(diào)制器的參數(shù)和結(jié)構(gòu)，并運用MALTAB和Simulink進行了建模和仿真驗證，確定Σ-Δ調(diào)制器為三位量化的單環(huán)三階CIFB (Cascade-of-integrators, feed-back form)結(jié)構(gòu)，過采樣率為256。其次是數(shù)字抽取濾波器，根據(jù)Σ-Δ調(diào)制器的性能要求選擇了數(shù)字抽取濾波器的結(jié)構(gòu)與類型，整個抽取濾波器采用梳狀濾波器和兩級半帶濾波器級聯(lián)的結(jié)構(gòu)實現(xiàn)。依據(jù)系統(tǒng)性能的要求，在MALTAB中設(shè)計了梳狀濾波器和半帶濾波器。最后，在Simulink中搭建了多位Σ-Δ模數(shù)轉(zhuǎn)換器的系統(tǒng)模型并進行了仿真，由仿真結(jié)果可知，本文所設(shè)計的多位Σ-Δ模數(shù)轉(zhuǎn)換器有效位數(shù)為24bit，信噪比為144dB，驗證了多位量化結(jié)構(gòu)的合理性。 通過對多位Σ-Δ模數(shù)轉(zhuǎn)換器的系統(tǒng)級設(shè)計，確定了Σ-Δ調(diào)制器和數(shù)字抽取濾波器的設(shè)計參數(shù)及結(jié)構(gòu)，依據(jù)這些參數(shù)，選擇合適的器件和運算放大器，通過分立元器件對Σ-Δ調(diào)制器進行了電路設(shè)計，包括三階積分器、3bit量化器和3bit反饋DAC；在FPGA上進行了數(shù)字抽取濾波器的實現(xiàn)，編寫了數(shù)字抽取濾波器的Verilog代碼。
[Abstract]:危-螖 A / D converters are widely used in video, multimedia, seismic survey instruments, sonar, electronic measurement and medium resolution systems because of their good linearity, high accuracy and low power consumption. At present, the high precision 危-螖 A / D conversion technology with multi-bit quantization is a hot topic, but the research on ADC in China is still in its infancy. The research and design level of 危-螖 A / D converter architecture is quite different from that of foreign advanced level. We need to strengthen the R & D of 危-螖 A / D converter and study 危-螖 A / D converter with independent intellectual property rights. Therefore, the research on the technology of multi-bit 危-螖 A / D conversion is of great significance in both academic and economic aspects. In this paper, the basic principle and structure of 危-螖 converter and the key technology in the design of multi bit quantization 危-螖 A / D converter are described in detail. On the basis of studying the various structures of 危-螖 A / D converter, the multibit quantization structure is emphatically studied, and the relationship between the bit number of multi bit quantizer and the precision of 危-螖 A / D converter is discussed. A 24-bit multibit 危-螖 A / D converter is designed by using the multibit 危-螖 ADC technology. In the process of system-level design, the first is the system design of 危-螖 modulator. According to the relevant knowledge of 危-螖 modulator, the parameters and structure of 危-螖 modulator are determined, and the modeling and simulation are done by using MALTAB and Simulink. It is determined that the 危-螖 modulator is a three-bit quantized single-ring third-order CIFB (Cascade-of-integrators, feed-back form) structure with a over-sampling rate of 256. Secondly, digital decimation filter. According to the performance requirement of 危-螖 modulator, the structure and type of digital decimation filter are selected. The whole decimation filter is realized by the structure of comb filter and two-stage half-band filter cascade. According to the requirement of system performance, comb filter and half band filter are designed in MALTAB. Finally, the system model of multi-bit 危-螖 A / D converter is built and simulated in Simulink. The simulation results show that the effective bit number and signal-to-noise ratio of the designed multi bit 危-螖 A / D converter are 24 bits and 144 dB, which verifies the rationality of the multibit quantization structure. The design parameters and structure of 危-螖 modulator and digital decimation filter are determined by the system-level design of multi-bit 危-螖 A / D converter. According to these parameters, appropriate devices and operational amplifiers are selected. The circuit of 危-螖 modulator is designed by discrete components, including third-order integrator, 3bit quantizer and 3bit feedback DAC;. The digital decimation filter is implemented on FPGA, and the Verilog code of digital decimation filter is written.
【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN792
本文編號：2268563
[Abstract]:危-螖 A / D converters are widely used in video, multimedia, seismic survey instruments, sonar, electronic measurement and medium resolution systems because of their good linearity, high accuracy and low power consumption. At present, the high precision 危-螖 A / D conversion technology with multi-bit quantization is a hot topic, but the research on ADC in China is still in its infancy. The research and design level of 危-螖 A / D converter architecture is quite different from that of foreign advanced level. We need to strengthen the R & D of 危-螖 A / D converter and study 危-螖 A / D converter with independent intellectual property rights. Therefore, the research on the technology of multi-bit 危-螖 A / D conversion is of great significance in both academic and economic aspects. In this paper, the basic principle and structure of 危-螖 converter and the key technology in the design of multi bit quantization 危-螖 A / D converter are described in detail. On the basis of studying the various structures of 危-螖 A / D converter, the multibit quantization structure is emphatically studied, and the relationship between the bit number of multi bit quantizer and the precision of 危-螖 A / D converter is discussed. A 24-bit multibit 危-螖 A / D converter is designed by using the multibit 危-螖 ADC technology. In the process of system-level design, the first is the system design of 危-螖 modulator. According to the relevant knowledge of 危-螖 modulator, the parameters and structure of 危-螖 modulator are determined, and the modeling and simulation are done by using MALTAB and Simulink. It is determined that the 危-螖 modulator is a three-bit quantized single-ring third-order CIFB (Cascade-of-integrators, feed-back form) structure with a over-sampling rate of 256. Secondly, digital decimation filter. According to the performance requirement of 危-螖 modulator, the structure and type of digital decimation filter are selected. The whole decimation filter is realized by the structure of comb filter and two-stage half-band filter cascade. According to the requirement of system performance, comb filter and half band filter are designed in MALTAB. Finally, the system model of multi-bit 危-螖 A / D converter is built and simulated in Simulink. The simulation results show that the effective bit number and signal-to-noise ratio of the designed multi bit 危-螖 A / D converter are 24 bits and 144 dB, which verifies the rationality of the multibit quantization structure. The design parameters and structure of 危-螖 modulator and digital decimation filter are determined by the system-level design of multi-bit 危-螖 A / D converter. According to these parameters, appropriate devices and operational amplifiers are selected. The circuit of 危-螖 modulator is designed by discrete components, including third-order integrator, 3bit quantizer and 3bit feedback DAC;. The digital decimation filter is implemented on FPGA, and the Verilog code of digital decimation filter is written.
【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN792
【引證文獻】
相關(guān)碩士學(xué)位論文 前3條
1 王海博;一種低功耗高精度Δ-∑調(diào)制器的設(shè)計[D];云南大學(xué);2016年
2 張道;基于FPGA的土壤數(shù)據(jù)采集系統(tǒng)[D];西北師范大學(xué);2015年
3 王婷;用于加速度計中的單環(huán)四階∑△調(diào)制器設(shè)計[D];齊齊哈爾大學(xué);2015年
本文編號：2268563
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