YHFT-Matrix編譯器向量化技術(shù)的研究與實(shí)現(xiàn)
發(fā)布時(shí)間:2018-05-28 06:12
本文選題:YHFT-Matrix + 自動(dòng)向量化 ; 參考:《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文
【摘要】:隨著多媒體和數(shù)字信號(hào)處理領(lǐng)域的飛速發(fā)展,需要更高性能的DSP來滿足計(jì)算需求。YHFT-Matrix是一款具有自主知識(shí)產(chǎn)權(quán)的高性能32位DSP處理器,具有特有的體系結(jié)構(gòu)和創(chuàng)新的指令集,屬于國家核高基重大專項(xiàng)重點(diǎn)工程項(xiàng)目。YHFT-Matrix采用VLIW體系架構(gòu),支持SIMD(single instruction multipledata)指令,具有規(guī)模大、功能全、綜合運(yùn)算性能高等特點(diǎn)。Matrix編譯器的向量部件能夠有效提升YHFT-Matrix芯片的處理性能。 論文實(shí)現(xiàn)了YHFT-Matrix體系結(jié)構(gòu)的SIMD指令自動(dòng)向量化技術(shù),但由于自動(dòng)向量化方法并不能完全滿足YHFT-Matrix的需求,論文進(jìn)一步研究并實(shí)現(xiàn)了基于編譯指導(dǎo)的向量化技術(shù)和基于內(nèi)聯(lián)函數(shù)的向量化技術(shù),這兩項(xiàng)向量化技術(shù)與SIMD指令自動(dòng)向量化技術(shù)一起構(gòu)建了Matrix編譯器的向量化技術(shù)體系。 論文首先對(duì)現(xiàn)今編譯器向量化技術(shù)的研究現(xiàn)狀進(jìn)行了分析,并分析了YHFT-Matrix體系結(jié)構(gòu)和指令集特點(diǎn),論文的主要工作如下: 1.實(shí)現(xiàn)了SIMD指令的自動(dòng)向量化技術(shù)。建立了Matrix編譯器的向量后端,按照其指令集的特點(diǎn),描述了向量指令,對(duì)向量寄存器、機(jī)器模式和向量長度進(jìn)行了擴(kuò)展。本文實(shí)現(xiàn)的SIMD指令自動(dòng)向量化有效提升了Matrix編譯器的向量化處理能力,并有效降低了編譯器的程序報(bào)錯(cuò)率。 2.實(shí)現(xiàn)了基于編譯指導(dǎo)的向量化技術(shù)。針對(duì)SIMD指令自動(dòng)向量化技術(shù)無法滿足Matrix編譯器向量化要求的情況,本文在YHFT-Matrix編譯器中設(shè)計(jì)并實(shí)現(xiàn)了兩類編譯指導(dǎo)控制向量化函數(shù)的方法,幫助向量化相關(guān)函數(shù)識(shí)別可以進(jìn)行向量化的程序信息,并引導(dǎo)向量化相關(guān)函數(shù)對(duì)這些程序信息進(jìn)行向量化處理操作。 3.實(shí)現(xiàn)了基于內(nèi)聯(lián)函數(shù)的向量化技術(shù),并用此技術(shù)在Matrix編譯器上實(shí)現(xiàn)了IR算法的向量化運(yùn)算。根據(jù)內(nèi)聯(lián)函數(shù)的向量化技術(shù)修改IIR算法的向量化程序,通過Matrix編譯器編譯產(chǎn)生其目標(biāo)代碼,,并將目標(biāo)代碼導(dǎo)入到Y(jié)HFT-Matrix DSP芯片中執(zhí)行,并將執(zhí)行結(jié)果與在CCS中TMS320C6713上執(zhí)行的模擬結(jié)果進(jìn)行了對(duì)比,實(shí)驗(yàn)結(jié)果表明了IIR算法的向量化運(yùn)算無誤高效,同時(shí)也證明了基于內(nèi)聯(lián)函數(shù)的向量化技術(shù)是正確有效的。 Matrix編譯器是以GCC-4.7.0為基礎(chǔ)移植開發(fā)的,本文在Matrix編譯器上實(shí)現(xiàn)了上述工作并進(jìn)行了驗(yàn)證,結(jié)果表明Matrix編譯器的向量化技術(shù)方法正確有效,所做工作有效提高了YHFT-Matrix編譯器的向量化性能。
[Abstract]:With the rapid development of multimedia and digital signal processing, higher performance DSP is needed to meet the computing requirements. YHFT-Matrix is a high performance 32-bit DSP processor with its own intellectual property rights, with unique architecture and innovative instruction set. YHFT-Matrix, a key project of the National Nuclear High Base Project, uses VLIW architecture to support the SIMD(single instruction multiple data (SIMD(single instruction) instruction, with large scale and full function. The vector component of the matrix compiler can effectively improve the processing performance of YHFT-Matrix chip. In this paper, the SIMD instruction automatic vectorization technology of YHFT-Matrix architecture is implemented, but the automatic vectorization method can not fully meet the requirements of YHFT-Matrix. This paper further studies and implements the vectorization technology based on compiler guidance and the vectorization technology based on inline function. These two vectorization techniques are combined with SIMD instruction automatic vectorization technology to construct the vectorization technology system of Matrix compiler. Firstly, this paper analyzes the current research status of compiler vectorization technology, and analyzes the characteristics of YHFT-Matrix architecture and instruction set. The main work of this paper is as follows: 1. The automatic vectorization technology of SIMD instruction is realized. The vector back end of the Matrix compiler is established. According to the characteristics of its instruction set, the vector instruction is described, and the vector register, machine mode and vector length are extended. The SIMD instruction automatic vectorization implemented in this paper effectively improves the vectorization processing ability of the Matrix compiler and effectively reduces the program error rate of the compiler. 2. The vectorization technology based on compiler guidance is realized. In view of the fact that automatic vectorization of SIMD instruction can not meet the requirements of Matrix compiler, this paper designs and implements two kinds of compile-guided control vectoring functions in YHFT-Matrix compiler. It helps to identify the program information that can be vectorized by the vectoring correlation function, and guides the vectoring correlation function to vectorize the program information. 3. The vectorization technique based on inline function is implemented, and the vectorization of IR algorithm is implemented on Matrix compiler. According to the vectorization technique of inline function, the vectorization program of IIR algorithm is modified, and the target code is compiled by Matrix compiler to produce its target code, and the target code is imported into YHFT-Matrix DSP chip to execute. The experimental results show that the vectorization operation of the IIR algorithm is correct and efficient, and that the vectorization technique based on inline function is correct and effective. The Matrix compiler is developed on the basis of GCC-4.7.0. This paper implements and verifies the above work on the Matrix compiler. The results show that the vectorization technique of the Matrix compiler is correct and effective. The work has effectively improved the vectorization performance of YHFT-Matrix compiler.
【學(xué)位授予單位】:國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2013
【分類號(hào)】:TP314
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