本文選題：AVS標(biāo)準(zhǔn)　切入點(diǎn)：H.264標(biāo)準(zhǔn)　出處：《山東大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：H.264/AVC是由國(guó)際電信聯(lián)盟和運(yùn)動(dòng)圖像專家組聯(lián)合制定的新一代視頻壓縮標(biāo)準(zhǔn),被認(rèn)為是當(dāng)前最具影響力的視頻標(biāo)準(zhǔn)。AVS標(biāo)準(zhǔn)是我國(guó)具有自主知識(shí)產(chǎn)權(quán)的第二代信源編碼標(biāo)準(zhǔn),近年得到國(guó)家的大力推廣。在未來(lái)這兩種標(biāo)準(zhǔn)必將互相融合,共同發(fā)展。熵編碼是AVS和H.264中都采用的無(wú)損壓縮編碼技術(shù),可以極大減小碼流的冗余度,因此設(shè)計(jì)同時(shí)兼容這兩種標(biāo)準(zhǔn)的雙模熵解碼器具有重要意義。 本文首先對(duì)AVS及H.264標(biāo)準(zhǔn)進(jìn)行研究并比較了其異同,然后詳細(xì)分析了其中采用的熵編碼算法,提出了AVS及H.264雙模熵解碼器的硬件結(jié)構(gòu),使其既支持AVS的CA-2D-VLC解碼,又支持H.264的CAVLC解碼和CABAC解碼,增強(qiáng)了通用性。該結(jié)構(gòu)復(fù)用了碼流緩沖移位和指數(shù)哥倫布解碼等模塊,從而減小電路資源消耗；對(duì)AVS碼表進(jìn)行壓縮優(yōu)化,對(duì)H.264的碼表進(jìn)行了分割重組,降低了碼表復(fù)雜度,提高了碼表索引效率；采用了流水線結(jié)構(gòu)加快了解碼速度；使用組合邏輯電路查找碼表,避免了對(duì)存儲(chǔ)器的訪問,減少了不必要的時(shí)序花銷；CAVLC解碼模塊將Coffetoken解碼與拖尾系數(shù)符號(hào)解碼壓縮在一個(gè)周期完成,并在解碼Runbefore的同時(shí)重組殘差塊,節(jié)約了解碼時(shí)鐘；提出了高效的CABAC解碼模塊結(jié)構(gòu),采用雙口RAM存儲(chǔ)上下文模型,并設(shè)計(jì)了高效的算術(shù)解碼計(jì)算模塊,提高了CABAC解碼速度。 本文采用Verilog HDL完成了雙模熵解碼器的寄存器傳輸級(jí)設(shè)計(jì),并根據(jù)AVS標(biāo)準(zhǔn)參考軟件RM52j和H.264標(biāo)準(zhǔn)參考軟件JM9.4建立了C參考模型。使用數(shù)字仿真工具VCS對(duì)熵解碼器進(jìn)行了功能仿真,并與參考模型的輸出進(jìn)行比對(duì),驗(yàn)證了設(shè)計(jì)的正確性。采用TSMC的0.13um工藝庫(kù),通過Synopsys公司的Design Compiler邏輯綜合工具對(duì)設(shè)計(jì)進(jìn)行邏輯綜合,結(jié)果表明該解碼器可工作在77MHz時(shí)鐘頻率下,滿足對(duì)4CIF、720p HD等格式視頻的實(shí)時(shí)解碼。最后采用形式驗(yàn)證工具Formality對(duì)綜合生成的門級(jí)網(wǎng)表進(jìn)行了形式驗(yàn)證。 驗(yàn)證和綜合結(jié)果表明,該雙模熵解碼器達(dá)到了本課題的設(shè)計(jì)目標(biāo)。
[Abstract]:H.264 / AVC is a new generation video compression standard developed jointly by the International Telecommunication Union and the Motion Image expert Group. It is considered to be the most influential video standard. AVS is the second generation source coding standard with independent intellectual property rights in China. In the future, the two standards will be merged and developed together. Entropy coding is a lossless compression coding technique used in both AVS and H.264, which can greatly reduce the redundancy of the code stream. So it is important to design two-mode entropy decoders compatible with these two standards. In this paper, the AVS and H.264 standards are studied and compared, then the entropy coding algorithm is analyzed in detail, and the hardware structure of AVS and H.264 dual-mode entropy decoder is proposed to support the CA-2D-VLC decoding of AVS. It also supports the CAVLC decoding and CABAC decoding of H.264, and enhances the generality. The structure reuses several modules, such as stream buffer shift and exponential Columbus decoding, to reduce the consumption of circuit resources, and optimizes the compression of the AVS code table. The code table of H.264 is segmented and reorganized, which reduces the complexity of the code table and improves the efficiency of the code table index. Pipeline structure is used to speed up the decoding speed, and the combinational logic circuit is used to find the code table, thus avoiding the access to the memory. The Coffetoken decoding and trailing coefficient symbol decoding are compressed in one cycle, and the residual block is recombined while decoding the Runbefore, thus saving the decoding clock, and an efficient CABAC decoding module structure is proposed. The dual-port RAM memory context model is adopted and an efficient arithmetic decoding calculation module is designed to improve the speed of CABAC decoding. In this paper, the register transfer level of dual-mode entropy decoder is designed by using Verilog HDL, and the C reference model is established according to AVS standard reference software RM52j and H.264 standard reference software JM9.4. The function of entropy decoder is simulated with the digital simulation tool VCS. Compared with the output of the reference model, the correctness of the design is verified. The design is synthesized by Design Compiler logic synthesis tool of Synopsys Company by using 0.13um process library of TSMC. The results show that the decoder can work at 77MHz clock frequency. It satisfies the real-time decoding of 4CIF-720p HD format video. Finally, the gate network table generated by the synthesis is verified by the formal verification tool Formality. The verification and synthesis results show that the dual-mode entropy decoder achieves the design goal.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TN919.8;TN764

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本文編號(hào)：1568080