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二維圖形加速引擎設(shè)計與實現(xiàn)

發(fā)布時間:2018-02-02 01:30

  本文關(guān)鍵詞: GPU 圖形加速 2D圖形 水平線 反走樣 FPGA 出處:《湖南大學》2013年碩士論文 論文類型:學位論文


【摘要】:在現(xiàn)代圖形視頻顯示系統(tǒng)中,將圖形處理任務(wù)從CPU中分離出來交由圖形處理器(Graphics Processing Unit,GPU)加速處理,已成為整個圖形顯控系統(tǒng)的基本結(jié)構(gòu)隨著計算機硬件水平的提升,以及集成電路制造技術(shù)和工藝水平的進步,圖形處理器在結(jié)構(gòu)和性能上也有了很大發(fā)展,并在航空航海醫(yī)療儀器測量儀器移動通信等多個領(lǐng)域的嵌入式終端得到了廣泛的應(yīng)用當前,圖形處理器技術(shù)主要由一些國際芯片巨頭所壟斷,國內(nèi)對于圖形處理器的應(yīng)用和研究相對國際先進水平還有較大差距因此,研究擁有自主知識產(chǎn)權(quán)的國產(chǎn)圖形處理器,尤其是應(yīng)用在嵌入式領(lǐng)域的圖形處理器具有十分重要的現(xiàn)實意義和實用價值 本文以圖形水平線填充的方式,設(shè)計了一個2D圖形加速引擎,用于實現(xiàn)直線三角形橢圓等基本2D圖形的繪制主要工作如下: 首先,研究圖形加速系統(tǒng)的基本結(jié)構(gòu),設(shè)計了2D圖形加速引擎的架構(gòu),詳細闡述了各功能模塊之間的聯(lián)系及其實現(xiàn)方法 其次,對于二維圖形基本算法進行研究,選擇適合于硬件實現(xiàn)的算法,由Verilog硬件描述語言完成各圖元模塊的代碼設(shè)計這些算法包括圖元預處理單元的裁剪算法一般直線段生成的Bresenham算法直線段反走樣的加權(quán)區(qū)域采樣算法橢圓的中點生成算法三角形填充算法和塊拷貝等 最后,在Modelsim環(huán)境下,對各個設(shè)計模塊進行功能仿真,驗證了設(shè)計的正確性對于整個2D圖形加速引擎進行了FPGA實物驗證,,并對其繪圖性能進行了分析驗證結(jié)果表明,二維圖形加速模塊能夠很好的與其它控制模塊兼容,顯著提高嵌入式系統(tǒng)的圖形處理速度
[Abstract]:In modern graphic video display system, graphics processing task is separated from CPU and handed over to graphics Processing Unit. GPU) accelerated processing has become the basic structure of the whole graphics display and control system with the improvement of the computer hardware level, as well as the progress of IC manufacturing technology and process level. Graphics processor (GPU) has also made great progress in structure and performance, and has been widely used in many fields, such as mobile communication of aviation and navigation medical instruments, measuring instruments, mobile communication and so on. The GPU technology is mainly monopolized by some international chip giants, so there is still a big gap between the application and research of GPU in China compared with the international advanced level. It is of great practical significance and practical value to study the domestic graphics processors with independent intellectual property rights, especially those used in the embedded field. In this paper, a 2D graphics acceleration engine is designed to realize the drawing of basic 2D graphics such as linear triangle ellipse and so on. The main work is as follows: First of all, the basic structure of graphics acceleration system is studied, the structure of 2D graphics acceleration engine is designed, and the relationship between each functional module and its implementation method are described in detail. Secondly, the basic algorithm of two-dimensional graphics is studied, and the algorithm suitable for hardware implementation is selected. Code design of each element module is accomplished by Verilog hardware description language. These algorithms include the clipping algorithm of the element preprocessing unit, the Bresenham algorithm which is generated by the general line segment, and the anti-aliasing algorithm of the line segment. The midpoint generation algorithm of ellipse in weighted region sampling algorithm triangle filling algorithm block copy and so on. Finally, in the Modelsim environment, the functional simulation of each design module, verify the correctness of the design for the entire 2D graphics acceleration engine for the FPGA physical verification. The results show that the 2D graphics acceleration module is compatible with other control modules, and the graphics processing speed of embedded system can be improved significantly.
【學位授予單位】:湖南大學
【學位級別】:碩士
【學位授予年份】:2013
【分類號】:TP391.41

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