數(shù)字陣列雷達擴展目標回波模擬技術(shù)研究與實現(xiàn)
發(fā)布時間：2019-02-17 07:52
【摘要】：隨著雷達信號處理技術(shù)的不斷發(fā)展以及雷達系統(tǒng)硬件實現(xiàn)平臺處理能力的不斷提高,更大陣元規(guī)模和信號處理帶寬的有源相控陣數(shù)字陣列雷達系統(tǒng)不斷出現(xiàn),其角度分辨率和距離分辨率隨之顯著提高。傳統(tǒng)的點目標單通道雷達回波模擬系統(tǒng)已經(jīng)不能有效地滿足系統(tǒng)各項指標的模擬測試要求,急需多通道擴展目標回波模擬系統(tǒng)。本文針對上述需要研制了一款基于VPX總線架構(gòu),可應用于任意波形回波模擬的數(shù)字陣列雷達擴展目標回波模擬系統(tǒng)。本文主要工作如下:首先,開展了擴展目標散射中心建模及其角度閃爍計算分析,進而給出了 96通道擴展目標雷達回波模擬系統(tǒng)的實現(xiàn)方案。接著,開展了雷達回波模擬系統(tǒng)的研制,該系統(tǒng)采用高性能8核DSP——TMS320C6678與分布式Virtex-7 + Kintex-7 FPGA的處理器架構(gòu),通過直接采樣中頻雷達發(fā)射信號,并根據(jù)上位機軟件的設(shè)定參數(shù),動態(tài)產(chǎn)生96通道中頻雷達接收回波模擬信號。回波模擬信號包括:基于多散射中心模型的擴展目標回波模擬信號、欺騙式干擾信號和高斯白噪聲信號等。整個雷達回波模擬系統(tǒng)采用VPX6U標準結(jié)構(gòu),由一塊高性能處理電路與三塊高速DAC陣列電路組成,具有通用性和可擴展性強的特點。其中,高性能處理電路負責回波相關(guān)參數(shù)計算,用于產(chǎn)生單通道擴展目標回波信號與干擾信號。每塊高速DAC陣列電路根據(jù)高性能處理電路的參數(shù)計算結(jié)果與輸出的單通道目標回波及干擾信號,分別獨立產(chǎn)生32通道的中頻回波模擬信號。最后,在所研制的雷達回波模擬系統(tǒng)平臺上,完成了高性能處理電路與高速DAC陣列電路相關(guān)FPGA和DSP軟件程序的設(shè)計和實現(xiàn),并開展了系統(tǒng)基本功能和性能的測試驗證。初步測試結(jié)果表明所構(gòu)建的系統(tǒng)可以根據(jù)上位機軟件的參數(shù)設(shè)定,實時正確地產(chǎn)生任意發(fā)射波形的擴展目標回波信號與欺騙式干擾信號,相關(guān)參數(shù)計算準確。該雷達回波模擬系統(tǒng)可以作為數(shù)字陣列雷達中頻半實物仿真平臺,在擴充射頻發(fā)射通道和發(fā)射天線陣列后,還可以用于構(gòu)建完整的射頻半實物仿真系統(tǒng)。
[Abstract]:With the continuous development of radar signal processing technology and the improvement of radar system hardware implementation platform processing ability, the active phased array digital array radar system with larger array size and signal processing bandwidth is emerging. The angle resolution and range resolution are improved significantly. The traditional point target single channel radar echo simulation system can not meet the requirements of the simulation and test of the system indexes effectively, so the multi-channel extended target echo simulation system is urgently needed. In this paper, a digital array radar extended target echo simulation system based on VPX bus architecture is developed, which can be used in the simulation of arbitrary waveform echo. The main work of this paper is as follows: firstly, the modeling of extended target scattering center and the analysis of angle scintillation are carried out, and the implementation scheme of 96 channel extended target radar echo simulation system is presented. Then, the radar echo simulation system is developed. The system adopts the processor architecture of high performance 8-core DSP--TMS320C6678 and distributed Virtex-7 Kintex-7 FPGA, and transmits signals by direct sampling if radar. According to the set parameters of upper computer software, 96 channels if radar receive echo analog signal dynamically. The echo analog signals include the extended target echo analog signal based on the multi-scattering center model, the deception jamming signal and Gao Si white noise signal. The whole radar echo simulation system adopts VPX6U standard structure and consists of a high performance processing circuit and three high-speed DAC array circuits. It has the characteristics of universality and expansibility. The high performance processing circuit is responsible for the calculation of echo parameters and is used to generate single channel extended target echo signal and interference signal. Each high speed DAC array circuit generates 32 channel if echo analog signals independently according to the calculation results of the parameters of the high performance processing circuit and the output single channel target echo signal. Finally, on the platform of radar echo simulation system, the design and implementation of FPGA and DSP software related to high performance processing circuit and high speed DAC array circuit are completed, and the basic functions and performance of the system are tested and verified. The preliminary test results show that the system can generate the extended target echo signal and deceptive jamming signal of arbitrary transmitting waveform in real time according to the parameter setting of upper computer software. The calculation of relevant parameters is accurate. The radar echo simulation system can be used as an intermediate frequency hardware-in-the-loop simulation platform for digital array radar. After extending the RF transmission channel and antenna array, it can also be used to construct a complete RF hardware-in-the-loop simulation system.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN957.51
本文編號：2424923
[Abstract]:With the continuous development of radar signal processing technology and the improvement of radar system hardware implementation platform processing ability, the active phased array digital array radar system with larger array size and signal processing bandwidth is emerging. The angle resolution and range resolution are improved significantly. The traditional point target single channel radar echo simulation system can not meet the requirements of the simulation and test of the system indexes effectively, so the multi-channel extended target echo simulation system is urgently needed. In this paper, a digital array radar extended target echo simulation system based on VPX bus architecture is developed, which can be used in the simulation of arbitrary waveform echo. The main work of this paper is as follows: firstly, the modeling of extended target scattering center and the analysis of angle scintillation are carried out, and the implementation scheme of 96 channel extended target radar echo simulation system is presented. Then, the radar echo simulation system is developed. The system adopts the processor architecture of high performance 8-core DSP--TMS320C6678 and distributed Virtex-7 Kintex-7 FPGA, and transmits signals by direct sampling if radar. According to the set parameters of upper computer software, 96 channels if radar receive echo analog signal dynamically. The echo analog signals include the extended target echo analog signal based on the multi-scattering center model, the deception jamming signal and Gao Si white noise signal. The whole radar echo simulation system adopts VPX6U standard structure and consists of a high performance processing circuit and three high-speed DAC array circuits. It has the characteristics of universality and expansibility. The high performance processing circuit is responsible for the calculation of echo parameters and is used to generate single channel extended target echo signal and interference signal. Each high speed DAC array circuit generates 32 channel if echo analog signals independently according to the calculation results of the parameters of the high performance processing circuit and the output single channel target echo signal. Finally, on the platform of radar echo simulation system, the design and implementation of FPGA and DSP software related to high performance processing circuit and high speed DAC array circuit are completed, and the basic functions and performance of the system are tested and verified. The preliminary test results show that the system can generate the extended target echo signal and deceptive jamming signal of arbitrary transmitting waveform in real time according to the parameter setting of upper computer software. The calculation of relevant parameters is accurate. The radar echo simulation system can be used as an intermediate frequency hardware-in-the-loop simulation platform for digital array radar. After extending the RF transmission channel and antenna array, it can also be used to construct a complete RF hardware-in-the-loop simulation system.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN957.51
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