數(shù)字陣列雷達(dá)擴(kuò)展目標(biāo)回波模擬技術(shù)研究與實(shí)現(xiàn)
[Abstract]:With the continuous development of radar signal processing technology and the improvement of radar system hardware implementation platform processing ability, the active phased array digital array radar system with larger array size and signal processing bandwidth is emerging. The angle resolution and range resolution are improved significantly. The traditional point target single channel radar echo simulation system can not meet the requirements of the simulation and test of the system indexes effectively, so the multi-channel extended target echo simulation system is urgently needed. In this paper, a digital array radar extended target echo simulation system based on VPX bus architecture is developed, which can be used in the simulation of arbitrary waveform echo. The main work of this paper is as follows: firstly, the modeling of extended target scattering center and the analysis of angle scintillation are carried out, and the implementation scheme of 96 channel extended target radar echo simulation system is presented. Then, the radar echo simulation system is developed. The system adopts the processor architecture of high performance 8-core DSP--TMS320C6678 and distributed Virtex-7 Kintex-7 FPGA, and transmits signals by direct sampling if radar. According to the set parameters of upper computer software, 96 channels if radar receive echo analog signal dynamically. The echo analog signals include the extended target echo analog signal based on the multi-scattering center model, the deception jamming signal and Gao Si white noise signal. The whole radar echo simulation system adopts VPX6U standard structure and consists of a high performance processing circuit and three high-speed DAC array circuits. It has the characteristics of universality and expansibility. The high performance processing circuit is responsible for the calculation of echo parameters and is used to generate single channel extended target echo signal and interference signal. Each high speed DAC array circuit generates 32 channel if echo analog signals independently according to the calculation results of the parameters of the high performance processing circuit and the output single channel target echo signal. Finally, on the platform of radar echo simulation system, the design and implementation of FPGA and DSP software related to high performance processing circuit and high speed DAC array circuit are completed, and the basic functions and performance of the system are tested and verified. The preliminary test results show that the system can generate the extended target echo signal and deceptive jamming signal of arbitrary transmitting waveform in real time according to the parameter setting of upper computer software. The calculation of relevant parameters is accurate. The radar echo simulation system can be used as an intermediate frequency hardware-in-the-loop simulation platform for digital array radar. After extending the RF transmission channel and antenna array, it can also be used to construct a complete RF hardware-in-the-loop simulation system.
【學(xué)位授予單位】:南京理工大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2017
【分類號(hào)】:TN957.51
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