【摘要】：ADF4193作為一款頻率綜合器,主要在無線接收和發(fā)射單元中作為上變頻或者下變頻模塊的本地振蕩器使用。它的重點(diǎn)是環(huán)路帶寬開關(guān)技術(shù)確保了在某些應(yīng)用中調(diào)頻時(shí)間對(duì)于時(shí)隙間隔的要求,減少了電路的成本、復(fù)雜程度以及電路板面積和電磁兼容等問題。本文實(shí)現(xiàn)了一個(gè)基于ADF4193的鎖相環(huán)電路,目的在于輸出頻率在1640～1900Mhz的射頻信號(hào),并完成30us內(nèi)的快速跳頻。在電路設(shè)計(jì)方面,首先根據(jù)指定的指標(biāo)比如輸出頻率、功率、相位噪聲、跳頻時(shí)間等來進(jìn)行VC0和濾波器的選擇。再根據(jù)選擇的有源器件確定電源方案,并進(jìn)行電源芯片的選取和設(shè)計(jì)。最后根據(jù)相關(guān)的環(huán)路濾波器仿真軟件、配置字模擬軟件等工具進(jìn)行環(huán)路濾波器的設(shè)計(jì)和配置程序的編寫。器件選擇好后通過EDA工具(這里主要是用了 CADENCE ALLEGRO)來進(jìn)行原理圖的繪制,確保電氣連接的正確可靠。再根據(jù)原理圖進(jìn)行PCB的布局和走線。PCB完成后拿到制版廠進(jìn)行電路板的制作,并開展元器件的貼裝工作。電路板的實(shí)物完成后,利用實(shí)驗(yàn)儀表進(jìn)行相關(guān)指標(biāo)的測(cè)試,沒有達(dá)到預(yù)計(jì)要求的指標(biāo)通過綜合分析找到原因差別,并進(jìn)行調(diào)試和優(yōu)化工作,通過調(diào)試環(huán)路濾波器帶寬、衰減器衰減量、輸入輸出匹配等參數(shù)使電路性能達(dá)到最優(yōu)。本文最終完成了一個(gè)快速跳頻的鎖相環(huán)電路的設(shè)計(jì)和調(diào)試工作,在確保信號(hào)的穩(wěn)定度和相位噪聲的前提下,實(shí)現(xiàn)了頻率的快速跳變,減小了跳頻時(shí)間。并根據(jù)相關(guān)軟件的仿真和調(diào)試結(jié)果,對(duì)過程中出現(xiàn)的問題進(jìn)行了總結(jié)和分析。
[Abstract]:As a frequency synthesizer, ADF4193 is mainly used in wireless receiving and transmitting unit as local oscillator of up-conversion or down-conversion module. It focuses on the loop bandwidth switch technology to ensure the frequency modulation time requirements for slot spacing in some applications, reducing the cost of the circuit, complexity, circuit board area and electromagnetic compatibility, and so on. A phase-locked loop circuit based on ADF4193 is implemented in this paper. The purpose of this circuit is to output the RF signal of frequency in 1640~1900Mhz and to complete the fast frequency hopping in 30us. In the aspect of circuit design, the VC0 and filter are selected according to the specified parameters such as output frequency, power, phase noise, frequency hopping time and so on. Then, according to the selected active devices, the power supply scheme is determined, and the selection and design of the power chip is carried out. Finally, the design of loop filter and the programming of configuration program are carried out according to the simulation software of loop filter and the software of configuration word. After the device is selected, the EDA tool is used to draw the schematic diagram with CADENCE ALLEGRO) to ensure the correct and reliable electrical connection. Then according to the schematic diagram, the layout of PCB and wiring. PCB is taken to the plate-making factory to make the circuit board, and the assembly of components is carried out. After the physical completion of the circuit board, the experimental instrument is used to test the related indexes, and the cause difference is found by comprehensive analysis, and the debugging and optimization work is carried out, and the bandwidth of the loop filter is adjusted by debugging the loop filter bandwidth. The parameters of attenuator attenuation, input and output matching make the circuit performance optimal. In this paper, the design and debugging of a fast frequency hopping PLL circuit is finally completed. On the premise of ensuring the stability of the signal and the phase noise, the fast frequency hopping is realized and the frequency hopping time is reduced. According to the simulation and debugging results of related software, the problems in the process are summarized and analyzed.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN74

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相關(guān)期刊論文 前2條

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本文編號(hào)：2180767