本文選題：基片集成波導(dǎo)壓控振蕩器 + 基片集成波導(dǎo)諧振器�。� 參考：《東南大學(xué)》2017年碩士論文

【摘要】：現(xiàn)代雷達(dá)和導(dǎo)引系統(tǒng)要求發(fā)射信號(hào)具有低相位噪聲和高頻率穩(wěn)定度,這對(duì)本振信號(hào)源的技術(shù)指標(biāo)和小型化提出了極高要求。隨著晶體振蕩器技術(shù)的高速發(fā)展,現(xiàn)在我們很容易獲得頻率穩(wěn)定度極高、相位噪聲優(yōu)異、雜散電平良好的參考頻率源。但如何簡(jiǎn)潔、高效、穩(wěn)定的利用這些參考源設(shè)計(jì)微波鎖相振蕩源則是微波電路設(shè)計(jì)中面臨的挑戰(zhàn)。傳統(tǒng)鎖相源(PLL)通常采用數(shù)字鎖相環(huán)、倍頻鏈、取樣鎖相DRO等較成熟的電路形式來(lái)實(shí)現(xiàn)對(duì)參考源的跟蹤和擴(kuò)展。數(shù)字鎖相環(huán)電路簡(jiǎn)化好集成,但性能不夠好;倍頻鏈近端相噪好,但集成度低、底噪高;模擬取樣鎖相DRO能夠性能最好,但是由于DRO電路和取樣環(huán)路較復(fù)雜很難小型化。本論文對(duì)傳統(tǒng)取樣方案進(jìn)行改進(jìn),采用集成度更高的基片集成波導(dǎo)壓控振蕩器(SIWVC O)代替介質(zhì)壓控振蕩器(DRVCO),并結(jié)合多層PCB工藝和MCM技術(shù)減小取樣環(huán)路尺寸。論文首先討論了 SIWVCO設(shè)計(jì)原理和電路形式,采用電路模型仿真結(jié)合電磁場(chǎng)仿真的方案對(duì)SIWVCO電路進(jìn)行仿真和優(yōu)化,設(shè)計(jì)的SIWVCO集成度高、相位噪聲低;然后分析取樣鎖相源工作原理,采用多層PCB工藝結(jié)合MCM技術(shù)的方案設(shè)計(jì)了取樣電路。最后測(cè)試結(jié)果為在載波 12GHz 相位噪聲分別為-110dBc/Hz@lKHz,-120dBc/Hz@10KHz,-116dBc/Hz@100KHz,-130dBc/Hz@1MHz。
[Abstract]:Modern radar and guidance systems require low phase noise and high frequency stability of the transmitted signal, which puts forward very high requirements for the technical specifications and miniaturization of the local oscillator signal source. With the rapid development of crystal oscillator technology, it is easy to obtain reference frequency sources with high frequency stability, excellent phase noise and good stray level. However, how to use these reference sources to design microwave phase-locked oscillators is a challenge in microwave circuit design. The traditional PLL (PLL) usually uses digital phase-locked loop, frequency-doubling chain, sampling phase-locked DRO and other mature circuit forms to track and expand the reference source. The digital PLL circuit simplifies and integrates well, but the performance is not good enough; the near-end phase noise of the frequency doubling chain is good, but the integration level is low and the bottom noise is high; the analog sampling phase-locked DRO circuit has the best performance, but it is difficult to miniaturize the DRO circuit and the sampling loop because of the complexity of the DRO circuit and the sampling loop. In this paper, the traditional sampling scheme is improved by using a more integrated substrate integrated waveguide voltage controlled oscillator (SIWVC O) instead of the dielectric voltage controlled oscillator (DRVCOO), and combining the multi-layer PCB process and MCM technology to reduce the size of the sampling loop. Firstly, the design principle and circuit form of SIWVCO are discussed. The scheme of circuit model simulation and electromagnetic field simulation is used to simulate and optimize SIWVCO circuit. The designed SIWVCO circuit has high integration and low phase noise. Then, the principle of sampling phase-locked source is analyzed, and the sampling circuit is designed by using multi-layer PCB technology and MCM technology. The final test results show that the phase noise at 12GHz is -110dBc / Hz-lKHz-120dBc / Hz-10kHz / 10kHz-116dBc / HzR @ 100kHz-130dBc / Hzfuture 1MHz.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN752

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本文編號(hào)：2043657