本文關(guān)鍵詞： Zynq 視頻拼接 圖像拼接 高層次綜合 軟硬件協(xié)同設(shè)計　出處：《大連海事大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著數(shù)字視頻技術(shù)的快速發(fā)展,視頻圖像拼接技術(shù)成為計算機(jī)視覺領(lǐng)域重要的研究課題之一。目前,視頻圖像拼接技術(shù)在數(shù)字廣播、視頻監(jiān)控、虛擬現(xiàn)實(shí)和醫(yī)療影像等領(lǐng)域得到廣泛的應(yīng)用。由于視頻拼接技術(shù)要處理大量的圖像數(shù)據(jù),對處理速度要求高等問題,因此能夠研究出一套實(shí)時性好、功耗低、體積小的視頻拼接系統(tǒng)具有重要的實(shí)際意義。本系統(tǒng)采用的是Xilinx公司Zynq-7000系列全面可編程片上系統(tǒng)平臺,片內(nèi)集成了雙核ARM Cortex-A9處理器和Xilinx 7系列FPGA,且內(nèi)部有高速互聯(lián)結(jié)構(gòu),采用軟硬件協(xié)同設(shè)計方法,將圖像采集、視頻拼接、高清顯示集合到一個嵌入式系統(tǒng)中。與單一處理器如DSP、ARM、FPGA相比,這種方法既充分利用了 FPGA強(qiáng)大的并行運(yùn)算能力與豐富的邏輯資源,又結(jié)合了 ARM在搭建操作系統(tǒng)與實(shí)現(xiàn)復(fù)雜算法方面的優(yōu)點(diǎn)。本文主要工作有:(1)在搭載Zynq芯片的ZedBoard開發(fā)板上,構(gòu)建嵌入式Linux開發(fā)環(huán)境,包括啟動文件的制作,交叉編譯環(huán)境的搭建,OpenCV和Qt的安裝與移植。(2)利用Vivado高層次綜合工具(High-Level Synthesis,HLS)設(shè)計自定義硬件加速IP核,包括Harris角點(diǎn)檢測算法和圖像傅里葉變換的倒位序算法。(3)在Zynq芯片的可編程邏輯(Programmable Logic,PL)部分完成硬件工程的搭建,主要包括硬件加速IP核的掛載與配置、視頻圖像的直接存儲器存取(Video Direct Memory Access,VDMA)配置以及 HDMI 高清顯示控制。(4)在Zynq芯片的處理器系統(tǒng)(Processing System,PS)部分即ARM內(nèi)實(shí)現(xiàn)系統(tǒng)軟件設(shè)計,主要包括VDMA IP核和自定義硬件加速IP核的驅(qū)動程序設(shè)計,以及使用OpenCV函數(shù)庫和自定義硬件加速IP核實(shí)現(xiàn)視頻圖像采集以及視頻拼接功能。本設(shè)計采用軟硬件協(xié)同設(shè)計方法完成了基于Zynq實(shí)時視頻拼接系統(tǒng),具有開發(fā)周期短、實(shí)時性好、體積小、界面友好等特點(diǎn)。
[Abstract]:With the rapid development of digital video technology, video image mosaic technology has become one of the important research topics in the field of computer vision. At present, video image mosaic technology in digital broadcasting, video surveillance. Virtual reality and medical images have been widely used. Because video mosaic technology has to deal with a large number of image data, high speed of processing problems, so it can develop a set of real-time, low power consumption. The small size of the video splicing system is of great practical significance. This system uses the Xilinx Zynq-7000 series of comprehensive programmable chip system platform. The dual-core ARM Cortex-A9 processor and the Xilinx 7 series FPGA are integrated in the chip, and there is a high speed interconnection structure inside. The image is collected by using the method of hardware and software co-design. Video splicing, high-definition display set into an embedded system, compared with a single processor such as DSP ARMU FPGA. This method not only makes full use of FPGA's powerful parallel computing ability and rich logical resources. Combined with the advantages of ARM in building the operating system and implementing complex algorithms. The main work of this paper is: 1) on the ZedBoard development board with Zynq chip. Build the embedded Linux development environment, including the production of startup files, cross-build the environment. Installation and migration of OpenCV and QT. 2) make use of the Vivado high-level Synthesis. HLS) designs custom hardware-accelerated IP cores. It includes Harris corner detection algorithm and image Fourier transform inversion algorithm. 3) Programmable Logic in Zynq chip. PL) part completes the hardware engineering construction, mainly includes the hardware acceleration IP core mount and the configuration. Video Direct Memory Access is accessed by direct memory of video image. VDMA) configuration and HDMI HD display control. 4) processing System in the processor system of the Zynq chip. PS) part is the software design of the system in ARM, mainly including the VDMA IP core and the driver design of the custom hardware accelerated IP core. The function of video image acquisition and video splicing is realized by using OpenCV function library and self-defined hardware accelerated IP core. This design adopts the method of hardware and software co-design to complete real-time video mosaic based on Zynq. The system. Has the development cycle short, the real-time good, the volume is small, the interface friendly and so on characteristic.
【學(xué)位授予單位】：大連海事大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP391.41

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