本文關鍵詞：高速數(shù)傳調(diào)制解調(diào)器設計與實現(xiàn)　出處：《南京理工大學》2017年碩士論文　論文類型：學位論文

  更多相關文章： 高速 并行 調(diào)制 解調(diào) FPGA

【摘要】：隨著信息通信技術的飛速發(fā)展,對通信速率的要求越來越高,如今的通信系統(tǒng)已越來越難以滿足不斷增長的通信速率需求。在通信系統(tǒng)中,調(diào)制解調(diào)器的速率往往決定了整個系統(tǒng)的傳輸速率。因此對高速數(shù)傳調(diào)制解調(diào)器的研究已日益成為熱點。對于高速數(shù)傳調(diào)制解調(diào)器來說,其處理速率主要受限于其所使用芯片的時鐘頻率。若要突破這一限制,就需要將調(diào)制解調(diào)器傳統(tǒng)的串行結構改為并行結構。本文對此進行了研究,從而給出一套并行的高速數(shù)傳調(diào)制解調(diào)器方案。本文首先分析了高速數(shù)傳調(diào)制解調(diào)器的各方面細節(jié)對其速率和資源的影響,進而確定了調(diào)制方式、并行路徑數(shù)、接收機結構等一系列相關細節(jié),劃定了總體的方案框架。然后研究了調(diào)制解調(diào)器各步驟的理論和常用算法,重點研究了各步驟的并行實現(xiàn)算法,從而給出了各步驟的并行實現(xiàn)方案。其中調(diào)制器部分主要有并行的差分編碼、并行的時域成形濾波、免混頻的正交上變頻。解調(diào)器部分主要包括頻域匹配濾波、頻域定時相偏校正、通過增刪采樣點實現(xiàn)的定時頻偏校正、經(jīng)近似處理優(yōu)化的并行盲均衡、在極坐標系實現(xiàn)檢測和校正的載波同步以及改進的并行差分解碼。這些方案都能以較少的資源消耗實現(xiàn)相應功能,它們的Matlab和Modelsim仿真結果也顯示了方案的高效性。最后本文在FPGA開發(fā)板ML605上對該高速并行調(diào)制解調(diào)器系統(tǒng)進行了實驗測試,測試結果也表明該高速并行調(diào)制解調(diào)器性能良好。
[Abstract]:With the rapid development of information and communication technology, the communication rate of the increasingly high demand, communication system nowadays has become increasingly difficult to meet the growing demand. The rate of communication in a communication system, modem speed often determines the transmission rate of the whole system. So the research of high speed digital modem has become a hot issue for. High speed digital modem, the processing rate is mainly limited by the use of chip clock frequency. To overcome this limitation, we need the serial structure modem instead of the traditional parallel structure. This paper conducted a study, which gives a parallel high-speed digital modem scheme. This paper analyzes the impact of high speed the number of modems in all aspects of the details of the rate and resources, and to determine the modulation, parallel path number, receiver node Construction of a series of related details, delineation of the overall framework. And then study the various steps of the modem theory and algorithms, focuses on the parallel algorithm of each step, and gives the steps of the parallel program. The main line of the modulator part and the differential encoding, parallel time domain shaping filter orthogonal mixer free frequency. The demodulator includes matched filtering in frequency domain, the frequency domain phase timing offset correction, by adding or deleting the sampling points to achieve timing frequency offset correction, the approximate parallel blind equalization optimization, implementation of parallel finite difference code and carrier detection and correction of the synchronization and improved in the polar coordinate system. These programs are to achieve the corresponding function with less resource consumption, their Matlab and Modelsim simulation results show the efficiency of the scheme. Finally, based on the FPGA development board ML605 of the high speed and The system of the modem is tested, and the results also show that the high speed parallel modem has good performance.

【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN915.05

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