發(fā)布時(shí)間：2018-01-04 01:33

  本文關(guān)鍵詞：ATLAS sTGC前端電子學(xué)測(cè)試關(guān)鍵技術(shù)研究　出處：《中國(guó)科學(xué)技術(shù)大學(xué)》2017年博士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 前端電子學(xué) 測(cè)試信號(hào)源 FEB配置測(cè)試板 現(xiàn)場(chǎng)可編程邏輯門陣列

【摘要】：2012年,LHC上的ATLAS/CMS實(shí)驗(yàn)裝置發(fā)現(xiàn)了 Higgs,標(biāo)志著粒子物理基礎(chǔ)科學(xué)進(jìn)入了一個(gè)新的時(shí)代,LHC實(shí)驗(yàn)的下一步科學(xué)目標(biāo)是精確測(cè)定Higgs粒子及其與物質(zhì)場(chǎng)相互作用耦合,尋找超出標(biāo)準(zhǔn)模型以外的新粒子、新現(xiàn)象。為實(shí)現(xiàn)這一物理目標(biāo),LHC及其實(shí)驗(yàn)將于2018和2022年,分兩階段進(jìn)行Phase 1和Phase 2升級(jí),實(shí)驗(yàn)的探測(cè)器系統(tǒng)也將同步進(jìn)行相應(yīng)升級(jí),以確保在高能高亮度質(zhì)子對(duì)撞環(huán)境下有效采集數(shù)據(jù)和開(kāi)展物理分析。本論文以研制ATLAS Phase 1 Muon譜儀端蓋NSW sTGC新型探測(cè)器系統(tǒng)為需求,針對(duì)當(dāng)前前端板高密度、大通道數(shù)量(升級(jí)需要1536塊前端板,共322000通道),開(kāi)展前端電子學(xué)測(cè)試技術(shù)研究,并設(shè)計(jì)了 256通道測(cè)試信號(hào)源和FEB配置測(cè)試板。本文首先分析sTGC探測(cè)器前端電子學(xué)測(cè)試需求和測(cè)試方法,通過(guò)對(duì)測(cè)試信號(hào)源研究,模擬前端探測(cè)器的輸出信號(hào),著力解決大規(guī)模、多通道探測(cè)器測(cè)試信號(hào)生成關(guān)鍵技術(shù),為FEB提供不同工作模式的仿真信號(hào)來(lái)測(cè)試FEB的功能和性能,目前,可以提供六種模式的256路測(cè)試信號(hào),同時(shí),提供同步時(shí)鐘信號(hào)和脈沖觸發(fā)信號(hào),能與FEB構(gòu)成一個(gè)完整的測(cè)試系統(tǒng)。其次,針對(duì)新一代ASIC芯片測(cè)試和配置系統(tǒng)測(cè)試驗(yàn)證為需求,開(kāi)發(fā)FEB配置測(cè)試板,研究以SCA為核心的配置芯片對(duì)FEB關(guān)鍵芯片的配置,主要包含對(duì)VMM3和TDS2的配置,實(shí)現(xiàn)了多種接口標(biāo)準(zhǔn)和通信協(xié)議的開(kāi)發(fā)以及數(shù)據(jù)鏈路的驗(yàn)證等,為FEB原型板關(guān)鍵芯片配置和數(shù)據(jù)讀出提供技術(shù)參考,并為最終的系統(tǒng)配置提供技術(shù)驗(yàn)證和支持。最后,以這兩個(gè)板子為基礎(chǔ)構(gòu)建測(cè)試平臺(tái),該測(cè)試平臺(tái)提供探測(cè)器測(cè)試信號(hào)仿真、前端電子學(xué)讀出、系統(tǒng)配置來(lái)構(gòu)建完整測(cè)試方案。對(duì)FEB進(jìn)行了一系列測(cè)試,包括通道增益、閾值、基線測(cè)試等,其中測(cè)試信號(hào)源的注入測(cè)試能夠替代探測(cè)器提供觸發(fā)信號(hào),進(jìn)行FEB的功能驗(yàn)證。FEB配置測(cè)試板能夠完成與SCA的數(shù)據(jù)通信,實(shí)現(xiàn)了對(duì)SCA芯片接口的操作與控制,包括E-link、SPI、I2C、GPIO等,并成功配置了 VMM3和TDS2,同時(shí)驗(yàn)證了 TDS2的4.8Gbps的高速數(shù)據(jù)傳輸功能。FEB配置測(cè)試板還在CERN進(jìn)行了電子學(xué)集成測(cè)試,完成了與 Pad trigger和 Router 板的通信。論文的創(chuàng)新點(diǎn)主要有:1、多通道、高密度、可編程測(cè)試信號(hào)源研究,完成了測(cè)試方法和測(cè)試?yán)碚摲治?實(shí)現(xiàn)多樣式可控256路FEB板測(cè)試信號(hào)生成功能,提高了系統(tǒng)測(cè)試效率,構(gòu)建測(cè)試平臺(tái)并對(duì)其中的關(guān)鍵ASIC(VMM2)器件進(jìn)行測(cè)試,并給出測(cè)試結(jié)果。2、針對(duì)FEB關(guān)鍵技術(shù),設(shè)計(jì)FEB配置測(cè)試板,開(kāi)發(fā)了多種數(shù)據(jù)接口協(xié)議,實(shí)現(xiàn)了利用GBT-SCA芯片對(duì)VMM3、TDS2的配置,同時(shí)驗(yàn)證了 4.8Gbps的TDS數(shù)據(jù)讀出,測(cè)試結(jié)果表明現(xiàn)采用的技術(shù)能夠滿足將來(lái)FEB的實(shí)現(xiàn)需求。3、高速網(wǎng)絡(luò)數(shù)據(jù)傳輸技術(shù),研究并實(shí)現(xiàn)了基于FPGA的MAC層網(wǎng)絡(luò)數(shù)據(jù)傳輸技術(shù)和計(jì)算機(jī)網(wǎng)卡直接網(wǎng)絡(luò)編程方法,完成計(jì)算機(jī)與FPGA高速網(wǎng)絡(luò)通信,傳輸速度測(cè)試可達(dá)926Mbps。
[Abstract]:In 2012, the discovery of Higgs by the ATLAS/CMS experimental device on the LHC marked the beginning of a new era in the basic science of particle physics. The next scientific goal of the LHC experiment is to accurately determine the Higgs particles and their interaction with the material field, and to find new particles and new phenomena beyond the standard model. LHC and its experiments will be upgraded to Phase 1 and Phase 2 in two phases in 2018 and 2022, and the detector system will be upgraded simultaneously. In order to ensure the effective data collection and physical analysis in the environment of high energy and high brightness proton collision, the NSW of the end cap of ATLAS Phase 1 Muon spectrometer is developed in this paper. New sTGC detector system is required. Aiming at the high density of front-end board and the number of large channels (1536 front-end boards are needed for upgrading, a total of 322000 channels are needed, the research on front-end electronics testing technology is carried out. And designed 256-channel test signal source and FEB configuration test board. Firstly, this paper analyzes the sTGC detector front-end electronic testing requirements and testing methods, through the research of the test signal source. The output signal of the front-end detector is simulated to solve the key technology of large-scale multi-channel detector test signal generation. The simulation signal of different working mode is provided for FEB to test the function and performance of FEB. At present, it can provide six modes of 256-channel test signal, at the same time, provide synchronous clock signal and pulse trigger signal, and can form a complete test system with FEB. Secondly. To meet the requirements of the new generation of ASIC chip test and configuration system test verification, the FEB configuration test board is developed, and the configuration of the key FEB chip based on SCA is studied. It mainly includes the configuration of VMM3 and TDS2, the development of various interface standards and communication protocols, and the verification of data links. It provides technical reference for the key chip configuration and data readout of FEB prototype board, and provides technical verification and support for the final system configuration. Finally, the test platform is built on the basis of these two boards. The test platform provides detector test signal simulation, front-end electronic readout, system configuration to build a complete test scheme. A series of tests on FEB, including channel gain, threshold, baseline test, etc. The injection test of test signal source can replace the detector to provide trigger signal, and the function verification of FEB. Feb configuration test board can complete the data communication with SCA. The operation and control of SCA chip interface are realized, including the E-link SPI I I 2C PIO, and the VMM3 and TDS2 are configured successfully. At the same time, it is verified that TDS2's 4.8Gbps high-speed data transmission function. Feb configuration test board is also tested in CERN. The communication with Pad trigger and Router board is completed. The main innovation of this paper is: 1: 1, multi-channel, high-density, programmable test signal source research. The test method and test theory analysis are completed, and the test signal generation function of multi-style controllable 256-channel FEB board is realized, and the system test efficiency is improved. Build the test platform and test the key ASIC VMM2 device, and give the test result. 2. According to the key technology of FEB, design the FEB configuration test board. A variety of data interface protocols are developed to realize the configuration of VMM3TDS2 using GBT-SCA chip. At the same time, the 4.8 Gbps TDS data readout is verified. The test results show that the current technology can meet the future FEB implementation requirements. 3, high-speed network data transmission technology. The MAC layer network data transmission technology based on FPGA and the direct network programming method of computer network card are studied and realized. The communication between computer and FPGA high-speed network is completed. The transmission speed test can reach 926 Mbps.
【學(xué)位授予單位】：中國(guó)科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2017
【分類號(hào)】：O572.2

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