發(fā)布時間：2018-01-04 01:33

  本文關鍵詞：ATLAS sTGC前端電子學測試關鍵技術研究　出處：《中國科學技術大學》2017年博士論文　論文類型：學位論文

  更多相關文章： 前端電子學 測試信號源 FEB配置測試板 現(xiàn)場可編程邏輯門陣列

【摘要】：2012年,LHC上的ATLAS/CMS實驗裝置發(fā)現(xiàn)了 Higgs,標志著粒子物理基礎科學進入了一個新的時代,LHC實驗的下一步科學目標是精確測定Higgs粒子及其與物質場相互作用耦合,尋找超出標準模型以外的新粒子、新現(xiàn)象。為實現(xiàn)這一物理目標,LHC及其實驗將于2018和2022年,分兩階段進行Phase 1和Phase 2升級,實驗的探測器系統(tǒng)也將同步進行相應升級,以確保在高能高亮度質子對撞環(huán)境下有效采集數(shù)據(jù)和開展物理分析。本論文以研制ATLAS Phase 1 Muon譜儀端蓋NSW sTGC新型探測器系統(tǒng)為需求,針對當前前端板高密度、大通道數(shù)量(升級需要1536塊前端板,共322000通道),開展前端電子學測試技術研究,并設計了 256通道測試信號源和FEB配置測試板。本文首先分析sTGC探測器前端電子學測試需求和測試方法,通過對測試信號源研究,模擬前端探測器的輸出信號,著力解決大規(guī)模、多通道探測器測試信號生成關鍵技術,為FEB提供不同工作模式的仿真信號來測試FEB的功能和性能,目前,可以提供六種模式的256路測試信號,同時,提供同步時鐘信號和脈沖觸發(fā)信號,能與FEB構成一個完整的測試系統(tǒng)。其次,針對新一代ASIC芯片測試和配置系統(tǒng)測試驗證為需求,開發(fā)FEB配置測試板,研究以SCA為核心的配置芯片對FEB關鍵芯片的配置,主要包含對VMM3和TDS2的配置,實現(xiàn)了多種接口標準和通信協(xié)議的開發(fā)以及數(shù)據(jù)鏈路的驗證等,為FEB原型板關鍵芯片配置和數(shù)據(jù)讀出提供技術參考,并為最終的系統(tǒng)配置提供技術驗證和支持。最后,以這兩個板子為基礎構建測試平臺,該測試平臺提供探測器測試信號仿真、前端電子學讀出、系統(tǒng)配置來構建完整測試方案。對FEB進行了一系列測試,包括通道增益、閾值、基線測試等,其中測試信號源的注入測試能夠替代探測器提供觸發(fā)信號,進行FEB的功能驗證。FEB配置測試板能夠完成與SCA的數(shù)據(jù)通信,實現(xiàn)了對SCA芯片接口的操作與控制,包括E-link、SPI、I2C、GPIO等,并成功配置了 VMM3和TDS2,同時驗證了 TDS2的4.8Gbps的高速數(shù)據(jù)傳輸功能。FEB配置測試板還在CERN進行了電子學集成測試,完成了與 Pad trigger和 Router 板的通信。論文的創(chuàng)新點主要有:1、多通道、高密度、可編程測試信號源研究,完成了測試方法和測試理論分析,實現(xiàn)多樣式可控256路FEB板測試信號生成功能,提高了系統(tǒng)測試效率,構建測試平臺并對其中的關鍵ASIC(VMM2)器件進行測試,并給出測試結果。2、針對FEB關鍵技術,設計FEB配置測試板,開發(fā)了多種數(shù)據(jù)接口協(xié)議,實現(xiàn)了利用GBT-SCA芯片對VMM3、TDS2的配置,同時驗證了 4.8Gbps的TDS數(shù)據(jù)讀出,測試結果表明現(xiàn)采用的技術能夠滿足將來FEB的實現(xiàn)需求。3、高速網(wǎng)絡數(shù)據(jù)傳輸技術,研究并實現(xiàn)了基于FPGA的MAC層網(wǎng)絡數(shù)據(jù)傳輸技術和計算機網(wǎng)卡直接網(wǎng)絡編程方法,完成計算機與FPGA高速網(wǎng)絡通信,傳輸速度測試可達926Mbps。
[Abstract]:In 2012, the discovery of Higgs by the ATLAS/CMS experimental device on the LHC marked the beginning of a new era in the basic science of particle physics. The next scientific goal of the LHC experiment is to accurately determine the Higgs particles and their interaction with the material field, and to find new particles and new phenomena beyond the standard model. LHC and its experiments will be upgraded to Phase 1 and Phase 2 in two phases in 2018 and 2022, and the detector system will be upgraded simultaneously. In order to ensure the effective data collection and physical analysis in the environment of high energy and high brightness proton collision, the NSW of the end cap of ATLAS Phase 1 Muon spectrometer is developed in this paper. New sTGC detector system is required. Aiming at the high density of front-end board and the number of large channels (1536 front-end boards are needed for upgrading, a total of 322000 channels are needed, the research on front-end electronics testing technology is carried out. And designed 256-channel test signal source and FEB configuration test board. Firstly, this paper analyzes the sTGC detector front-end electronic testing requirements and testing methods, through the research of the test signal source. The output signal of the front-end detector is simulated to solve the key technology of large-scale multi-channel detector test signal generation. The simulation signal of different working mode is provided for FEB to test the function and performance of FEB. At present, it can provide six modes of 256-channel test signal, at the same time, provide synchronous clock signal and pulse trigger signal, and can form a complete test system with FEB. Secondly. To meet the requirements of the new generation of ASIC chip test and configuration system test verification, the FEB configuration test board is developed, and the configuration of the key FEB chip based on SCA is studied. It mainly includes the configuration of VMM3 and TDS2, the development of various interface standards and communication protocols, and the verification of data links. It provides technical reference for the key chip configuration and data readout of FEB prototype board, and provides technical verification and support for the final system configuration. Finally, the test platform is built on the basis of these two boards. The test platform provides detector test signal simulation, front-end electronic readout, system configuration to build a complete test scheme. A series of tests on FEB, including channel gain, threshold, baseline test, etc. The injection test of test signal source can replace the detector to provide trigger signal, and the function verification of FEB. Feb configuration test board can complete the data communication with SCA. The operation and control of SCA chip interface are realized, including the E-link SPI I I 2C PIO, and the VMM3 and TDS2 are configured successfully. At the same time, it is verified that TDS2's 4.8Gbps high-speed data transmission function. Feb configuration test board is also tested in CERN. The communication with Pad trigger and Router board is completed. The main innovation of this paper is: 1: 1, multi-channel, high-density, programmable test signal source research. The test method and test theory analysis are completed, and the test signal generation function of multi-style controllable 256-channel FEB board is realized, and the system test efficiency is improved. Build the test platform and test the key ASIC VMM2 device, and give the test result. 2. According to the key technology of FEB, design the FEB configuration test board. A variety of data interface protocols are developed to realize the configuration of VMM3TDS2 using GBT-SCA chip. At the same time, the 4.8 Gbps TDS data readout is verified. The test results show that the current technology can meet the future FEB implementation requirements. 3, high-speed network data transmission technology. The MAC layer network data transmission technology based on FPGA and the direct network programming method of computer network card are studied and realized. The communication between computer and FPGA high-speed network is completed. The transmission speed test can reach 926 Mbps.
【學位授予單位】：中國科學技術大學
【學位級別】：博士
【學位授予年份】：2017
【分類號】：O572.2

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