【摘要】：基于微處理器實現(xiàn)的數(shù)字PID(或者PI~λD~μ)控制器改變了傳統(tǒng)的模擬控制器不靈活的問題,但微處理器的復(fù)位時間長(達到ms級)以及現(xiàn)場環(huán)境惡劣的情況下易出現(xiàn)程序跑飛的問題,影響了控制系統(tǒng)的穩(wěn)定性和可靠性。FPGA特有的架構(gòu)可有效提高處理器的運行速度和復(fù)位時間,為分?jǐn)?shù)階PI~λD~μ控制器的實現(xiàn)提供一種有效的方法。針對分?jǐn)?shù)階PI~λD~μ控制器的數(shù)學(xué)表達式復(fù)雜,不易編程實現(xiàn)的問題,文中將分?jǐn)?shù)階PI~λD~μ控制器的表達式變形為矩陣相乘的形式,充分利用FPGA架構(gòu)中的查找表即根據(jù)輸入地址得到輸出數(shù)據(jù)(數(shù)據(jù)是預(yù)先計算后存入查找表),該算法可以提高分?jǐn)?shù)階PIλIμ控制器的計算速度和精度。論文采用Modelsim仿真,結(jié)果表明該算法實現(xiàn)精度的相對誤差小于0.3%,相對于傳統(tǒng)的方法具有較大的提高。構(gòu)建速度閉環(huán)控制系統(tǒng)來驗證分?jǐn)?shù)階PI~λD~μ控制器的性能。FPGA中實現(xiàn)的邏輯電路模塊主要包括電機測速模塊、PWM波產(chǎn)生模塊和分?jǐn)?shù)階PI~λD~μ控制器模塊。在電機測速模塊中,為了提高速度的測量精度和系統(tǒng)的動態(tài)性能,提出動態(tài)估算法實現(xiàn)電機的速度測量,針對控制信號的上升沿到第一個被測脈沖上升沿之間的不完整被測脈沖,利用小數(shù)估計不完整被測脈沖的思想,用前一個相鄰?fù)暾}沖來估算不完整被測脈沖值;利用直接數(shù)字合成技術(shù)(DDS)輸出鋸齒波作為載波產(chǎn)生PWM波進而控制電機;分?jǐn)?shù)階PI~λD~μ控制器主要由寄存器模塊、查找表模塊、計算系數(shù)矩陣A模塊和控制模塊等。論文對研究內(nèi)容進行編程并仿真驗證,結(jié)果表明各模塊的功能均達到了預(yù)計目標(biāo),速度測量結(jié)果的輸出滯后時間小于2us,實現(xiàn)了電機測速的高精度特征。本文研究與設(shè)計了分?jǐn)?shù)階PI~λD~μ控制器和基于動態(tài)估算法測量電機轉(zhuǎn)速,具有提高分?jǐn)?shù)階PI~λD~μ控制器的計算和速度測量的精度,減少分?jǐn)?shù)階PI~λD~μ控制器的計算時間和速度測量延遲等特點,有效提高了控制系統(tǒng)的動態(tài)性能,為分?jǐn)?shù)階PI~λD~μ控制器提供一種實現(xiàn)方法,具有較高的工程應(yīng)用價值。
[Abstract]:The digital PID (or PI~ 位 D ~ 渭) controller based on microprocessor has changed the traditional analog controller's inflexibility. However, the reset time of the microprocessor is long (up to ms level) and the problem of program running is easy to occur when the field environment is bad. The stability and reliability of the control system are affected. The unique architecture of FPGA can effectively improve the speed and reset time of the processor, and provide an effective method for the implementation of fractional order PI~ 位 D 渭 controller. Aiming at the problem that the mathematical expression of fractional order PI~ 位 D 渭 controller is complex and difficult to be realized by programming, the expression of fractional order PI~ 位 D 渭 controller is deformed into matrix multiplying form in this paper. By making full use of the look-up table in FPGA architecture, that is to say, the output data is obtained according to the input address (the data is stored in the look-up table), the algorithm can improve the calculation speed and accuracy of the fractional PI 位 I 渭 controller. The Modelsim simulation results show that the relative error of the algorithm is less than 0.3, which is higher than that of the traditional method. A speed closed loop control system is constructed to verify the performance of fractional order PI~ 位 D 渭 controller. The logic circuit modules implemented in FPGA mainly include motor speed measurement module, PWM wave generation module and fractional order PI~ 位 D 渭 controller module. In order to improve the accuracy of speed measurement and the dynamic performance of the system in the motor speed measurement module, a dynamic estimation method is proposed to realize the speed measurement of the motor. In view of the incomplete measured pulse between the rising edge of the control signal and the first measured pulse, the idea of estimating the incomplete measured pulse is used to estimate the incomplete measured pulse by the previous adjacent complete pulse. The direct digital synthesis technique (DDS) is used to output sawtooth wave as carrier to generate PWM wave and control motor. The fractional order PI~ 位 D 渭 controller is mainly composed of register module, lookup table module, calculation coefficient matrix A module and control module. The results show that the function of each module has reached the expected goal, and the output lag time of the velocity measurement result is less than 2 us. the high precision characteristic of motor speed measurement is realized. In this paper, the fractional-order PI~ 位 D渭 controller and the motor speed measurement based on dynamic estimation method are studied and designed, which can improve the accuracy of calculation and velocity measurement of fractional order PI~ 位 D渭 controller. The dynamic performance of the control system is improved effectively by reducing the calculation time and velocity measurement delay of the fractional order PI~ 位 D 渭 controller. It provides a realization method for the fractional order PI~ 位 D 渭 controller and has high engineering application value.
【學(xué)位授予單位】：安徽理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP273

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