極化碼性能研究及CA-SCL譯碼器的FPGA實現
發(fā)布時間：2018-08-24 15:39
【摘要】：隨著社會的進步,移動通信技術已進入5G新時代,極化碼(Polar Code)作為5G的熱門備選編碼方案正受到廣泛的關注和研究。近幾年來,雖然有成熟的Turbo碼和LDPC碼這些高效實用的信道編碼,但它們的誤碼性能與香農限存在一些差距,而極化碼是唯一在理論上證明能達到香農極限的編碼。目前,極化碼作為控制信道的編碼方案,已被寫入5G標準中。極化碼由Arikan在2008年發(fā)現并提出,其產生基礎是基于離散二進制無記憶信道(B-DMC)的極化現象,其編碼和譯碼均具有高效且易于實現的結構,因而具有很大的應用潛力。本文的主要研究了有限碼長下極化碼的碼字構造方法和譯碼算法,以及設計基于CA-SCL算法的譯碼器的硬件結構和FPGA實現。具體工作如下:首先介紹了現有的Turbo碼和LDPC碼這兩種可迭代的編碼,詳細介紹了它們的編譯碼結構和算法,仿真模擬了譯碼性能,指出Turbo碼會出現錯誤平臺現象,非規(guī)則LDPC碼的編碼復雜度高,最后介紹了極化碼,并從碼字構造、編碼和譯碼三個方面做比較,證明了極化碼的優(yōu)越性。其次詳細介紹了極化碼的產生原理,研究了信道分解和信道合并過程中發(fā)生信道極化時,BEC等信道模型的參數變化規(guī)律,仿真分析了極化定理的實質,并引出極化編碼理論。具體分析了生成矩陣的產生和編碼流程,并基于編碼原理研究了碼字構造方法,提出了針對不同信道環(huán)境的信息位選擇方法,對每種方法進行性能分析,結果表明高斯近似方法更具有實用價值。最后研究了Plotkin結構的RM碼與極化碼的異同。然后研究了極化碼的譯碼算法。在基礎SC算法上提出了運算改進型的LLR近似計算和性能改進型的SCL譯碼方法。SCL譯碼算法在SC的基礎上增加了多條路徑的選擇,使得算法性能接近于ML譯碼的性能,CA-SCL在SCL方法的基礎上增加了冗余校驗CRC碼,迭代譯碼時對輸出的序列進行CRC過濾,一旦某序列校驗和為零則直接作為譯碼結果輸出并停止迭代。CRC碼校驗進一步提高SCL算法的糾錯能力,將此方法作為最后硬件實現的譯碼方法。最后對CA-SCL譯碼器進行FPGA硬件結構的設計。針對CA-SCL譯碼的各個環(huán)節(jié),分別設計相關的子功能模塊,在QuartusII軟件上完成了verilog程序輸入,在Modelsim中完成功能仿真和調試,仿真成功后,在譯碼器頂層模塊得到譯碼的輸出結果。所設計的循環(huán)冗余SCL譯碼器在工作頻率300Mhz時達到6.5Mbps的吞吐率。
[Abstract]:With the development of society, mobile communication technology has entered a new era of 5G. Polarization code (Polar Code), as a popular alternative coding scheme of 5G, is receiving extensive attention and research. In recent years, although there are mature Turbo codes and LDPC codes as efficient and practical channel codes, there are some differences between their error performance and Shannon's limit, and polarization codes are the only codes that can reach Shannon's limit in theory. At present, polarization code, as a coding scheme of control channel, has been written into 5 G standard. Polarization code was discovered and proposed by Arikan in 2008. It is based on polarization phenomenon of discrete binary memoryless channel (B-DMC). Its coding and decoding are both efficient and easy to implement, so they have great application potential. This paper mainly studies the codeword construction and decoding algorithm of the polarization code with finite code length, and designs the hardware structure and FPGA implementation of the decoder based on CA-SCL algorithm. The main work is as follows: firstly, two kinds of iterative codes, Turbo code and LDPC code, are introduced, their encoding and decoding structures and algorithms are introduced in detail, the decoding performance is simulated, and the error platform phenomenon of Turbo code is pointed out. The coding complexity of irregular LDPC codes is high. Finally, the polarization codes are introduced, and the advantages of polarization codes are proved by comparing them from three aspects: code construction, coding and decoding. Secondly, the generation principle of polarization codes is introduced in detail, and the variation law of the parameters of channel models such as BEC when channel polarization occurs during channel decomposition and channel merging is studied. The essence of polarization theorem is simulated and the polarization coding theory is introduced. The generation and coding process of the generation matrix are analyzed in detail. Based on the coding principle, the codeword construction method is studied, and the information bit selection method for different channel environments is proposed, and the performance of each method is analyzed. The results show that the Gao Si approximation method is more practical. Finally, the similarities and differences between RM codes and polarimetric codes with Plotkin structure are studied. Then the decoding algorithm of polarization code is studied. Based on the basic SC algorithm, an improved LLR approximate algorithm and a performance modified SCL decoding algorithm are proposed. Based on the SC algorithm, the multiple paths are added to the algorithm. Making the performance of the algorithm close to that of ML decoding, CA-SCL adds redundancy check CRC code on the basis of SCL method, and filters the output sequence by CRC during iterative decoding. Once a sequence check sum is zero, it is output directly as decoding result and the iterative. CRC code check is stopped to further improve the error-correcting ability of SCL algorithm. This method is used as the final decoding method implemented by hardware. Finally, the FPGA hardware structure of CA-SCL decoder is designed. For each link of CA-SCL decoding, the related sub-function modules are designed, the verilog program input is completed on the QuartusII software, and the function simulation and debugging are completed in the Modelsim. After the simulation is successful, the decoding output results are obtained in the decoder top-level module. The designed cyclic redundant SCL decoder achieves the 6.5Mbps throughput at the operating frequency 300Mhz.
【學位授予單位】：南京航空航天大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN911.22
本文編號：2201269
[Abstract]:With the development of society, mobile communication technology has entered a new era of 5G. Polarization code (Polar Code), as a popular alternative coding scheme of 5G, is receiving extensive attention and research. In recent years, although there are mature Turbo codes and LDPC codes as efficient and practical channel codes, there are some differences between their error performance and Shannon's limit, and polarization codes are the only codes that can reach Shannon's limit in theory. At present, polarization code, as a coding scheme of control channel, has been written into 5 G standard. Polarization code was discovered and proposed by Arikan in 2008. It is based on polarization phenomenon of discrete binary memoryless channel (B-DMC). Its coding and decoding are both efficient and easy to implement, so they have great application potential. This paper mainly studies the codeword construction and decoding algorithm of the polarization code with finite code length, and designs the hardware structure and FPGA implementation of the decoder based on CA-SCL algorithm. The main work is as follows: firstly, two kinds of iterative codes, Turbo code and LDPC code, are introduced, their encoding and decoding structures and algorithms are introduced in detail, the decoding performance is simulated, and the error platform phenomenon of Turbo code is pointed out. The coding complexity of irregular LDPC codes is high. Finally, the polarization codes are introduced, and the advantages of polarization codes are proved by comparing them from three aspects: code construction, coding and decoding. Secondly, the generation principle of polarization codes is introduced in detail, and the variation law of the parameters of channel models such as BEC when channel polarization occurs during channel decomposition and channel merging is studied. The essence of polarization theorem is simulated and the polarization coding theory is introduced. The generation and coding process of the generation matrix are analyzed in detail. Based on the coding principle, the codeword construction method is studied, and the information bit selection method for different channel environments is proposed, and the performance of each method is analyzed. The results show that the Gao Si approximation method is more practical. Finally, the similarities and differences between RM codes and polarimetric codes with Plotkin structure are studied. Then the decoding algorithm of polarization code is studied. Based on the basic SC algorithm, an improved LLR approximate algorithm and a performance modified SCL decoding algorithm are proposed. Based on the SC algorithm, the multiple paths are added to the algorithm. Making the performance of the algorithm close to that of ML decoding, CA-SCL adds redundancy check CRC code on the basis of SCL method, and filters the output sequence by CRC during iterative decoding. Once a sequence check sum is zero, it is output directly as decoding result and the iterative. CRC code check is stopped to further improve the error-correcting ability of SCL algorithm. This method is used as the final decoding method implemented by hardware. Finally, the FPGA hardware structure of CA-SCL decoder is designed. For each link of CA-SCL decoding, the related sub-function modules are designed, the verilog program input is completed on the QuartusII software, and the function simulation and debugging are completed in the Modelsim. After the simulation is successful, the decoding output results are obtained in the decoder top-level module. The designed cyclic redundant SCL decoder achieves the 6.5Mbps throughput at the operating frequency 300Mhz.
【學位授予單位】：南京航空航天大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN911.22
【參考文獻】
相關碩士學位論文 前2條
1 鄭芝芳;基于Polar碼的OFDM系統(tǒng)圖像傳輸的應用研究[D];南京郵電大學;2012年
2 楊秀云;非理想協作通信系統(tǒng)及其聯合迭代譯碼性能的研究[D];南京航空航天大學;2010年
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