本文選題：TD-LTE + PDSCH　； 參考：《電子科技大學(xué)》2016年碩士論文

【摘要】：無線技術(shù)的快速發(fā)展對硬件平臺的性能有了越來越高的要求,為支持多種無線標(biāo)準(zhǔn),TI推出了基于KeyStone I架構(gòu)的多核DSP TMS320C6670。除了四個頻率高達(dá)1.2GHz的DSP處理芯片外,TMS320C6670還集成了多種硬件加速器,用于減輕DSP處理器的處理需求。本文研究了基于TMS320C6670多核DSP平臺的TD-LTE下行鏈路典型物理信道的實(shí)現(xiàn)與測試。論文主要研究了TD-LTE下行鏈路中的兩個信道,下行共享信道(Physical Downlink Shared Channel,PDSCH)與廣播信道(Physical Broadcast Channel,PBCH)。論文分析和研究了PDSCH和PBCH的傳輸原理,對處理流程進(jìn)行子模塊劃分,對關(guān)鍵模塊進(jìn)行算法選型;運(yùn)用Matlab搭建了鏈路級浮點(diǎn)仿真平臺,將發(fā)端輸出數(shù)據(jù)與第三方提供的標(biāo)準(zhǔn)數(shù)據(jù)進(jìn)行對比,驗(yàn)證了發(fā)端處理流程的正確性。論文在高斯信道下進(jìn)行了鏈路的性能仿真,驗(yàn)證了算法方案的可行性,也為基于DSP的定點(diǎn)實(shí)現(xiàn)提供了性能參考。論文重點(diǎn)研究了基于TMS320C6670芯片的多用戶PDSCH和PBCH的實(shí)現(xiàn)關(guān)鍵技術(shù)。論文研究了下行多用戶數(shù)據(jù)的發(fā)送過程,包括基于位協(xié)處理器(Bit Coprocessor,BCP)的比特級數(shù)據(jù)處理、多天線處理及端口映射、基于傅里葉變換協(xié)處理器(Fast Fourier Transformation Coprocessor,FFTC)的快速傅里葉變換。為實(shí)現(xiàn)峰值速率下的下行PDSCH多天線數(shù)據(jù)接收,論文分析并設(shè)計了四核聯(lián)合的數(shù)據(jù)流水線處理過程,包括基于FFTC的分符號傅里葉變換、數(shù)據(jù)提取和分離、基于最小二乘和線性內(nèi)插的信道估計、基于最小二乘的信道均衡、軟解調(diào)、解擾、基于BCP的解速率匹配、利用Turbo譯碼協(xié)處理器(Turbo-Decoder Coprocessor,TCP3D)的譯碼以及CRC校驗(yàn)。論文研究了PBCH的盲檢過程。由于PBCH解析時,該子幀在40ms周期內(nèi)的相對位置和天線端口數(shù)目未知,PBCH接收端需要多次盲檢以獲得接入系統(tǒng)所需的信息。因此,論文詳細(xì)分析了盲檢過程和復(fù)雜度,并進(jìn)行了DSP的軟件實(shí)現(xiàn)。論文分析驗(yàn)證了實(shí)現(xiàn)方案資源分配的可行性;通過逐模塊的數(shù)據(jù)比對和性能測試驗(yàn)證了模塊實(shí)現(xiàn)的有效性和正確性;為充分測試系統(tǒng)性能,論文將鏈路與Matlab浮點(diǎn)仿真鏈路進(jìn)行了誤比特率性能對比,驗(yàn)證鏈路定點(diǎn)實(shí)現(xiàn)的性能。論文設(shè)計了下行鏈路聯(lián)調(diào)方案,結(jié)合FPGA、射頻板完成了下行鏈路的收發(fā)聯(lián)調(diào)測試,測試平臺經(jīng)信道模擬器完成了性能和穩(wěn)定性測試。
[Abstract]:With the rapid development of wireless technology, the performance of hardware platform is becoming more and more important. In order to support various wireless standards, TI has introduced a multi-core DSP TMS320C6670 based on KeyStone I architecture. In addition to four DSP processing chips with a frequency of up to 1.2 GHz, TMS320C6670 also integrates a variety of hardware accelerators to reduce the processing requirements of DSP processors. This paper studies the realization and test of typical physical channel of TD-LTE downlink based on TMS320C6670 multi-core DSP platform. In this paper, two channels in TD-LTE downlink, physical Downlink shared Channel (PDSCH) and physical broadcast Channel (PBCH) are studied. This paper analyzes and studies the transmission principle of PDSCH and PBCH, divides the processing flow into sub-modules, selects the key modules, builds a link level floating-point simulation platform with Matlab. The correctness of the process is verified by comparing the output data with the standard data provided by the third party. In this paper, the performance simulation of the link in Gao Si channel is carried out, which verifies the feasibility of the algorithm and provides a performance reference for the fixed-point implementation based on Gao Si. This paper focuses on the implementation of multi-user PDSCH and PBCH based on TMS320C6670 chip. The transmission process of downlink multiuser data is studied in this paper, including bit Coprocessor (BCP) based bit-level data processing, multi-antenna processing and port mapping, and Fast Fourier transform (FFT) based on Fast Fourier Transformation processor (FFTC). In order to realize the downlink PDSCH multi-antenna data receiving at the peak rate, this paper analyzes and designs the data pipeline processing process of the four-core union, including the split-symbol Fourier transform based on FFTC, data extraction and separation. Channel estimation based on least squares and linear interpolation, channel equalization based on least squares, soft demodulation, descrambling, rate matching based on BCP, decoding and CRC checking by Turbo decoding coprocessor (Turbo-Decoder processor TCP3D). The blind detection process of PBCH is studied in this paper. Because the relative position of the sub-frame and the number of antenna ports in the 40ms cycle are unknown, the PBCH receiver needs multiple blind checks to obtain the information needed for the access system. Therefore, the paper analyzes the blind detection process and complexity in detail, and carries out the software implementation of DSP. The paper analyzes and verifies the feasibility of realizing the resource allocation of the scheme; validates the validity and correctness of the module by module data comparison and performance testing; in order to fully test the system performance, In this paper, the link is compared with Matlab floating-point simulation link to verify the performance of link fixed-point implementation. In this paper, the downlink joint scheme is designed. Combined with FPGA, the radio frequency board completes the downlink transceiver test, and the test platform completes the performance and stability test through the channel simulator.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN929.5

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