發(fā)布時(shí)間：2018-05-14 20:40

  本文選題：DC-DC變換器 + 可外同步��； 參考：《西南交通大學(xué)》2017年碩士論文

【摘要】：隨著電子系統(tǒng)的發(fā)展和進(jìn)步,應(yīng)用需求增多促使互聯(lián)網(wǎng),物聯(lián)網(wǎng)和信息安全密碼系統(tǒng)大力發(fā)展。各種不同功能的芯片被集成在一個(gè)系統(tǒng)中,其對(duì)電源要求各不相同,為了減少相互之間的影響,增加系統(tǒng)的穩(wěn)定性,就要求電源芯片能夠有更強(qiáng)的兼容性。本文針對(duì)以上問(wèn)題,利用了鎖相環(huán)技術(shù)來(lái)外同步DC-DC變換器的時(shí)鐘頻率,并且設(shè)計(jì)實(shí)現(xiàn)一種應(yīng)用于可外同步DC-DC變換器的電荷泵鎖相環(huán)電路。首先介紹了本文研究的背景和意義,指出了電源管理芯片市場(chǎng)情況和發(fā)展趨勢(shì)。介紹了電源管理芯片中DC-DC變換器的開(kāi)關(guān)頻率對(duì)其性能的影響,并且給出了利用鎖相環(huán)技術(shù)的可外同步變換器的優(yōu)勢(shì)。同時(shí)還介紹了鎖相環(huán)電路的結(jié)構(gòu)和相關(guān)指標(biāo),分析了兩類(lèi)鎖相環(huán)的動(dòng)態(tài)特性。然后分別給出了本文電荷泵鎖相環(huán)的具體實(shí)現(xiàn)電路,對(duì)電荷泵電路進(jìn)行了優(yōu)化設(shè)計(jì),加入基準(zhǔn)源保證了電荷泵的充電和放電電流的穩(wěn)定性,并且基準(zhǔn)源還能為后續(xù)的電路提供偏置電流和比較的基準(zhǔn)閾值電壓。設(shè)計(jì)了具體的壓控振蕩器電路,其增益可以隨著外同步頻率而改變,減小了系統(tǒng)的鎖定時(shí)間。并且其控制電壓被限定在指定范圍內(nèi)。最后本文基于TSMC 0.18um CMOS的工藝模型,利用Candence軟件進(jìn)行了具體電路圖的繪制并且利用Hspice軟件對(duì)各個(gè)子電路和整體電路進(jìn)行了仿真驗(yàn)證。仿真結(jié)果表明,在3V的電源電壓供電情況下,本文的電荷泵鎖相可以在TT,SS,FF三個(gè)工藝角下和-20℃到120℃溫度范圍內(nèi)同步頻率為500KHz到2MHz的外部時(shí)鐘,鎖定時(shí)間最大為68us最小為27us,功耗小于223.8uW。并且系統(tǒng)能夠在壓控振蕩器的控制電壓在0.68V到1.14V之外時(shí)屏蔽外部時(shí)鐘。電路的指標(biāo)都滿(mǎn)足預(yù)期,在DC-DC變換器等應(yīng)用中有很高的實(shí)用價(jià)值。
[Abstract]:With the development and progress of electronic system, the Internet of things, Internet of things and information security cryptosystem are greatly developed. In order to reduce the influence of each other and increase the stability of the system, the power chip is required to be more compatible. In order to solve the above problems, this paper uses phase-locked loop (PLL) technology to synchronize the clock frequency of DC-DC converter, and designs and implements a charge pump phase-locked loop (CPPLL) circuit which can be applied to extrinsic synchronous DC-DC converter. Firstly, the background and significance of this paper are introduced, and the market situation and development trend of power management chip are pointed out. The influence of switching frequency on the performance of DC-DC converter in power management chip is introduced, and the advantage of external synchronous converter using PLL technology is given. At the same time, the structure and related indexes of PLL circuit are introduced, and the dynamic characteristics of two kinds of PLL circuits are analyzed. Then, the realization circuit of the charge pump phase-locked loop is given respectively, and the charge pump circuit is optimized and the stability of charge and discharge current is ensured by adding the reference source. The reference source can also provide bias current and reference threshold voltage for subsequent circuits. A specific VCO circuit is designed. The gain can be changed with the external synchronization frequency and the locking time of the system is reduced. And its control voltage is limited to a specified range. Finally, based on the process model of TSMC 0.18um CMOS, the specific circuit diagram is drawn by using Candence software, and each sub-circuit and the whole circuit are simulated and verified by Hspice software. The simulation results show that the external clock of 500KHz to 2MHz can be synchronized with the phase locked phase of the charge pump in the three process angles and the temperature range from -20 鈩，

本文編號(hào)：1889386