本文選題：波控系統(tǒng) + CAN控制器�。� 參考：《強(qiáng)激光與粒子束》2017年09期

【摘要】：為實(shí)現(xiàn)相控陣天線波控系統(tǒng)小型化、芯片化的目的,設(shè)計(jì)了一種基于Avalon總線的CAN控制器IP核。參照CAN2.0B協(xié)議規(guī)范,給出了CAN控制器IP核的功能結(jié)構(gòu),利用Verilog硬件描述語(yǔ)言完成了控制器接口邏輯、位流處理器、位時(shí)序邏輯等模塊設(shè)計(jì),并進(jìn)行了設(shè)備驅(qū)動(dòng)及應(yīng)用軟件開(kāi)發(fā)。將設(shè)計(jì)的CAN控制器IP核、Nios II微處理器、多個(gè)單元相位控制器IP核等集成到FPGA中構(gòu)成子陣級(jí)波束控制的SoPC系統(tǒng)。最后對(duì)CAN總線的通信性能進(jìn)行了實(shí)驗(yàn)測(cè)試。結(jié)果表明:設(shè)計(jì)的CAN控制器IP核能夠在實(shí)際CAN網(wǎng)絡(luò)中穩(wěn)定可靠地收發(fā)數(shù)據(jù)�；谶@種方式構(gòu)建的系統(tǒng),擴(kuò)展方便、可移植性高、具有較強(qiáng)的適應(yīng)性,也可用于高密度、緊湊型工業(yè)控制領(lǐng)域。
[Abstract]:In order to realize the miniaturization and chip of phased array antenna wave control system, a CAN controller IP core based on Avalon bus is designed. According to the CAN2.0B protocol specification, the function structure of IP core of CAN controller is given. The controller interface logic, bit stream processor, bit timing logic and other modules are designed by using Verilog hardware description language, and the device driver and application software are developed. The designed CAN controller IP core nios II microprocessor and several cell phase controllers IP cores are integrated into FPGA to form a sub-array beam control SoPC system. Finally, the communication performance of CAN bus is tested experimentally. The results show that the IP core of the designed CAN controller can send and receive data stably and reliably in the real CAN network. The system based on this method has the advantages of convenient expansion, high portability, strong adaptability, and can also be used in the field of high-density, compact industrial control.
【作者單位】： 西南交通大學(xué)物理科學(xué)與技術(shù)學(xué)院;
【基金】：國(guó)家高技術(shù)發(fā)展計(jì)劃項(xiàng)目
【分類號(hào)】：TN821.8

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本文編號(hào)：1877379