本文選題：可重構(gòu)系統(tǒng) + 數(shù)據(jù)緩存結(jié)構(gòu)��； 參考：《上海交通大學(xué)學(xué)報(bào)》2017年05期

【摘要】：針對(duì)面向雷達(dá)應(yīng)用可重構(gòu)系統(tǒng)中數(shù)據(jù)訪(fǎng)存沖突嚴(yán)重、訪(fǎng)存效率低等問(wèn)題,設(shè)計(jì)了一種片上層次化緩存結(jié)構(gòu),并提出基于多存儲(chǔ)體的線(xiàn)性步長(zhǎng)可變的數(shù)據(jù)管理機(jī)制,通過(guò)建立計(jì)算陣列與各個(gè)存儲(chǔ)體之間可配置的邏輯映射關(guān)系,有效降低了多個(gè)計(jì)算陣列并行工作時(shí)產(chǎn)生的訪(fǎng)存沖突,提高了計(jì)算陣列的數(shù)據(jù)吞吐率,從而提高了可重構(gòu)系統(tǒng)的數(shù)據(jù)訪(fǎng)存性能.結(jié)果表明,該方案在有效控制硬件開(kāi)銷(xiāo)的同時(shí),極大地提升了可重構(gòu)系統(tǒng)的數(shù)據(jù)訪(fǎng)存性能,以256~64×210快速傅里葉變換為例,與經(jīng)典并行緩存機(jī)制相比,可重構(gòu)系統(tǒng)的數(shù)據(jù)訪(fǎng)存性能提升了26.09%~54.60%.
[Abstract]:In view of the serious conflict of data access in the radar application reconfigurable system and the low memory efficiency, an upper secondary cache structure is designed, and a variable data management mechanism based on the linear step length based on multi memory is proposed. By establishing the configurable logic mapping relationship between the computing array and each memory bank, the data management mechanism is effectively reduced. The memory access conflict caused by the parallel operation of multiple computing arrays improves the data throughput of the computing array and improves the data access performance of the reconfigurable system. The results show that the scheme greatly improves the data access performance of the reconfigurable system while controlling the hardware overhead effectively, and the 256~64 x 210 fast Fourier transform is used. For example, compared with classical parallel caching mechanism, the data access performance of reconfigurable system is improved by 26.09%~54.60%.

【作者單位】： 東南大學(xué)國(guó)家專(zhuān)用集成電路系統(tǒng)工程技術(shù)研究中心;
【基金】：國(guó)家自然科學(xué)基金項(xiàng)目(61404028,61204023) 國(guó)家高技術(shù)研究發(fā)展計(jì)劃(863)項(xiàng)目(2012AA012703)資助
【分類(lèi)號(hào)】：TN957

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