本文選題：極化碼　切入點(diǎn)：譯碼算法　出處：《山東科技大學(xué)》2017年碩士論文

【摘要】：現(xiàn)代社會(huì)中隨著數(shù)字通信技術(shù)的飛速發(fā)展,人們對(duì)數(shù)字通信系統(tǒng)的可靠性要求不斷提高,對(duì)高速數(shù)據(jù)傳輸?shù)男枨笠苍絹碓酱�。信道編碼是提升通信系統(tǒng)可靠性的有效方法,幾十年來,編碼學(xué)家一直在尋找可達(dá)香農(nóng)界的信道編碼方法。Arikan提出的極化碼是第一種能夠被嚴(yán)格證明達(dá)到信道容量的信道編碼方法,是信道編碼領(lǐng)域的重大突破。極化碼有較低的編譯碼復(fù)雜度,在未來數(shù)字通信系統(tǒng)中的應(yīng)用前景非常廣闊。本文對(duì)極化碼的串行抵消列表譯碼算法及其硬件實(shí)現(xiàn)進(jìn)行了具體的研究,主要工作如下:(1)深入研究和改進(jìn)極化碼的譯碼算法。詳細(xì)分析串行抵消(SC)譯碼算法的理論知識(shí)和譯碼特點(diǎn),進(jìn)一步研究了串行抵消列表(SCL)譯碼算法和多種增強(qiáng)的SCL譯碼算法,包括CA-SCL譯碼算法、aCA-SCL譯碼算法和PCA-SCL譯碼算法。設(shè)計(jì)躍進(jìn)式譯碼算法,降低譯碼延時(shí)。設(shè)計(jì)了自適應(yīng)的分段循環(huán)冗余校驗(yàn)輔助的SCL(aPCA-SCL)譯碼算法,仿真結(jié)果表明,aPCA-SCL譯碼算法相比aCA-SCL譯碼算法,在信噪比小于2dB時(shí)可降低11%-42%的平均搜索寬度。(2)對(duì)aPCA-SCL譯碼算法進(jìn)行硬件實(shí)現(xiàn)。首先調(diào)整算法以適合硬件實(shí)現(xiàn),設(shè)計(jì)合理的aPCA-SCL譯碼器硬件架構(gòu)。然后給出一種資源使用少、性能損失較小的量化方案,其中信道LLR位寬為4,中間值LLR位寬為6,PM值位寬為8。相比浮點(diǎn)性能曲線,性能損失小于O.1dB。最后詳細(xì)的介紹各模塊的硬件設(shè)計(jì),采用折疊式部分和結(jié)構(gòu)并加以改進(jìn)以適應(yīng)躍進(jìn)式譯碼算法,優(yōu)化排序網(wǎng)絡(luò)使速度提升35.43%,采用“Lazy Copy”技術(shù)降低路徑復(fù)制導(dǎo)致的大量資源浪費(fèi)。(3)完成aPCA-SCL譯碼器的功能仿真,并將aPCA-SCL譯碼器與極化碼測(cè)試鏈路、上位機(jī)結(jié)合,搭建了完整的測(cè)試系統(tǒng),完成FPGA驗(yàn)證和性能評(píng)估。驗(yàn)證結(jié)果表明,在碼長(zhǎng)N = 1024,碼率R = 1/2,分段數(shù)P = 2,最大搜索寬度Lmax=4時(shí),FPGA最高頻率為212.27 MHz,最高吞吐率可達(dá)114.22 Mbps。與PCA-SCL譯碼器相比,在誤幀率低于0.01時(shí),吞吐率提升27.56%以上。
[Abstract]:With the rapid development of digital communication technology in modern society, the demand for reliability of digital communication system is increasing, and the demand for high-speed data transmission is also increasing. Channel coding is an effective method to improve the reliability of communication system. For decades, encoders have been looking for a Shannon bound channel coding method. Arikan's polarimetric code is the first channel coding method that can be strictly proven to reach channel capacity. Polarimetric code is a great breakthrough in the field of channel coding. The application prospect in the future digital communication system is very broad. In this paper, the serial cancellation list decoding algorithm of polarization code and its hardware implementation are studied in detail. The main work is as follows: (1) the decoding algorithm of polarization code is studied and improved in depth. The theoretical knowledge and decoding characteristics of serial cancellation decoding algorithm are analyzed in detail, and the serial canceling list decoding algorithm and several enhanced SCL decoding algorithms are further studied. The algorithm includes CA-SCL decoding algorithm and PCA-SCL decoding algorithm. The algorithm of leap forward decoding is designed to reduce the decoding delay. An adaptive algorithm for decoding SCLLA PCA-SCL, which is assisted by piecewise cyclic redundancy check, is designed. The simulation results show that compared with the aCA-SCL decoding algorithm, the PCA-SCL decoding algorithm can reduce the average search width of 11% -42% when the SNR is less than 2dB. A reasonable hardware architecture of aPCA-SCL decoder is designed. Then a quantization scheme with less resource usage and less performance loss is presented, in which the channel LLR bit width is 4, the intermediate value LLR bit width is 6 渭 m bit width is 8. Compared with the floating point performance curve, The performance loss is less than 0.1 dB. Finally, the hardware design of each module is introduced in detail, and the folding partial sum structure is adopted and improved to adapt to the leap forward decoding algorithm. The optimized sorting network increases the speed by 35.43 steps, and uses "Lazy Copy" technology to reduce the waste of a lot of resources caused by path replication) to complete the functional simulation of aPCA-SCL decoder, and combine the aPCA-SCL decoder with the polarization code test link, and the host computer. A complete test system is built to complete FPGA verification and performance evaluation. The verification results show that, When the code length N = 1024, the code rate R = 1 / 2, the number of segments P = 2, the maximum search width Lmax= 4, the maximum frequency of FPGA is 212.27 MHz, and the maximum throughput can reach 114.22 Mbps.Compared with the PCA-SCL decoder, the throughput is increased by more than 27.56% when the frame error rate is less than 0.01.
【學(xué)位授予單位】：山東科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN911.22

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 倪磊;極化碼編譯碼算法研究及譯碼算法FPGA實(shí)現(xiàn)[D];哈爾濱工業(yè)大學(xué);2016年

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本文編號(hào)：1679652