本文關(guān)鍵詞： 寬帶無(wú)線通信 模擬基帶 信道選擇濾波器 可編程增益放大器 直流失調(diào)　出處：《東南大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：本文面向?qū)拵o(wú)線通信發(fā)射機(jī),設(shè)計(jì)了其中的模擬基帶電路,該模擬基帶電路主要包括三個(gè)關(guān)鍵模塊,它們分別是信道選擇濾波器、可編程增益放大器(PGA)和直流失調(diào)消除電路(DCOC)。本文從直接上變頻發(fā)射機(jī)的架構(gòu)出發(fā),確定了模擬基帶整體和三個(gè)關(guān)鍵模塊的設(shè)計(jì)指標(biāo),并完成了信道選擇濾波器、PGA和DCOC等關(guān)鍵模塊的設(shè)計(jì)。本文設(shè)計(jì)的信道選擇濾波器為六階切比雪夫Active-RC低通濾波器,采用三個(gè)單位增益的Sallen-Key 二階單元級(jí)聯(lián)的方式實(shí)現(xiàn),濾波器的截止頻率可通過(guò)電容陣列進(jìn)行調(diào)節(jié)。二階單元中的運(yùn)算放大器采用雙輸入對(duì)的全差分兩級(jí)運(yùn)算放大器,一對(duì)輸入用于構(gòu)成濾波器,另一對(duì)輸入用于構(gòu)成單位增益負(fù)反饋。運(yùn)算放大器的第一級(jí)采用改進(jìn)的共源共柵負(fù)載,以提高運(yùn)算放大器閉環(huán)后的共模穩(wěn)定性。本文的可編程增益放大器分為衰減級(jí)和放大級(jí),衰減級(jí)采用π型電阻網(wǎng)絡(luò)實(shí)現(xiàn),對(duì)于放大級(jí)的實(shí)現(xiàn),本文選擇基于源極退化電阻可編程的PGA作為基本結(jié)構(gòu)�？紤]到傳統(tǒng)的源極退化電阻可編程的PGA的線性度和增益之間的矛盾,本文將一種跨導(dǎo)增強(qiáng)技術(shù)應(yīng)用于PGA放大級(jí)的核心電路,以提高PGA的增益和線性度。對(duì)于直流失調(diào)電壓的問(wèn)題,本文采用了低通負(fù)反饋的方式進(jìn)行直流失調(diào)消除。負(fù)反饋通路中的低通濾波器采用一階RC濾波器實(shí)現(xiàn),其中的大電容通過(guò)米勒效應(yīng)在片實(shí)現(xiàn)。DCOC的輸出級(jí)為4個(gè)跨導(dǎo)單元,其中2個(gè)跨導(dǎo)單元流出動(dòng)態(tài)電流,另外2個(gè)流入動(dòng)態(tài)電流,這個(gè)電流在反饋電阻上產(chǎn)生電壓用于抵消直流失調(diào)。考慮到版圖對(duì)電路性能的影響,本文給出了版圖設(shè)計(jì)的流程和基本原則,重點(diǎn)分析了版圖設(shè)計(jì)的匹配原則,并根據(jù)上述原則完成了模擬基帶電路的版圖設(shè)計(jì)。該模擬基帶電路采用TSMC0.13μm CMOS工藝實(shí)現(xiàn),且已經(jīng)通過(guò)后仿真驗(yàn)證。后仿真結(jié)果表明,模擬基帶電路在電源電壓1.2V下的功耗小于22mW,帶寬可以在100MHz、130MHz和170MHz三個(gè)檔位調(diào)節(jié),可實(shí)現(xiàn)步長(zhǎng)為1dB的增益步進(jìn)調(diào)節(jié),調(diào)節(jié)的范圍為-18～30dB�？梢钥闯�,電路后仿真結(jié)果滿足寬帶系統(tǒng)對(duì)模擬基帶電路的設(shè)計(jì)要求,可以應(yīng)用于寬帶無(wú)線通信發(fā)射機(jī)中。
[Abstract]:In this paper, the analog baseband circuit for broadband wireless communication transmitter is designed. The analog baseband circuit consists of three key modules, which are channel selection filters. Programmable gain Amplifier (PGA) and DC offset Elimination Circuit (DCOC). Based on the architecture of direct up-conversion transmitter, the design indexes of the whole analog baseband and three key modules are determined in this paper. The key modules of channel selection filter, such as PGA and DCOC, are designed. The channel selection filter designed in this paper is a sixth-order Chebyshev Active-RC low-pass filter, which is implemented by cascading Sallen-Key second-order units with three unit gains. The cutoff frequency of the filter can be adjusted by a capacitor array. The operational amplifier in the second order unit uses a fully differential two-stage operational amplifier with two input pairs, and a pair of inputs is used to form the filter. The other pair of inputs are used to form negative feedback of unit gain. The first stage of the operational amplifier adopts an improved common-gate load to improve the common-mode stability after the closed loop of the operational amplifier. The programmable gain amplifier in this paper is divided into attenuation stage and amplifying stage. The attenuation stage is realized by 蟺 type resistor network. For the realization of amplifier stage, a programmable PGA based on the source degenerate resistor is chosen as the basic structure. Considering the contradiction between the linearity and gain of the traditional source degenerate resistor programmable PGA, In this paper, a transconductance enhancement technique is applied to the core circuit of PGA amplifier to improve the gain and linearity of PGA. The low pass filter in the negative feedback path is realized by the first order RC filter. The output stage of the DCOC is 4 transconductance units, which are realized by Hans Muller effect. Two of the transconductors flow out of the dynamic current and the other two flow into the dynamic current, which generates a voltage on the feedback resistor to counteract the DC offset. This paper gives the flow and basic principles of layout design, analyzes the matching principle of layout design, and completes the layout design of analog baseband circuit according to the above principles. The analog baseband circuit is realized by TSMC0.13 渭 m CMOS process. The simulation results show that the power consumption of the analog baseband circuit is less than 22mW at 1.2V supply voltage, the bandwidth can be adjusted at 100MHz / 100MHz and 170MHz, and the gain step adjustment of 1dB can be realized. It can be seen that the simulation results after the circuit can meet the design requirements of the analog baseband circuit in the broadband system, and can be used in the broadband wireless communication transmitter.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN830;TN92

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