本文關(guān)鍵詞： HART FSK 分組排序 調(diào)制解調(diào) 低功耗 相位連續(xù)　出處：《沈陽工業(yè)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：HART協(xié)議是可尋址遠程變送器數(shù)據(jù)通道協(xié)議的簡稱,是美國Rosement公司于1985年推出的一種用于現(xiàn)場智能儀表和控制室設(shè)備之間雙向通信的協(xié)議規(guī)程。HART協(xié)議物理層使用FSK(頻移鍵控)調(diào)制解調(diào)技術(shù),在4mA-20mA模擬信號上疊加一個幅度為0.5mA均值為0的數(shù)字信號,以1200Hz和2200Hz交流信號分別代替數(shù)字信號的“1”和“0”,使模擬通信和數(shù)字通信同時進行且互不干擾。HART協(xié)議屬于模擬系統(tǒng)向數(shù)字系統(tǒng)轉(zhuǎn)變過程中的過渡產(chǎn)品,因此在當前的過渡時期具有較強的市場競爭能力,得到了較快的發(fā)展。本論文介紹了一種基于國外工藝設(shè)計的HART協(xié)議芯片,設(shè)計通過采用逆向分析的方法,結(jié)合HART協(xié)議標準。首先通過使用Chip Logic網(wǎng)表提取器對版圖照片進行認清器件和數(shù)字邏輯門,并且把各個器件和邏輯門根據(jù)線網(wǎng)連接起來。然后根據(jù)芯片使用說明書對各個功能模塊電路圖進行整理,在整理數(shù)字電路時,從門級到RTL級的深層次分析是尤其困難的,而且費時費力,本論文提出了一種分組排序的數(shù)字電路深層次分析方法,大大縮短了分析時間。最后選用國內(nèi)工藝根據(jù)所學(xué)理論知識并結(jié)合說明書對電路進行工藝移植,并利用相關(guān)軟件對功能模塊進行仿真驗證,對于一些不滿足原設(shè)計要求的模塊將進行再設(shè)計。各個模塊通過仿真驗證之后,將各個模塊連接起來再整體仿真驗證。通過前期電路提取和后期功能模塊整理以及對功能模塊進行分析,整個HART協(xié)議芯片總共分為調(diào)制電路,解調(diào)電路,公共電路三個部分。這三個部分是整個電路的關(guān)鍵部分,所以對于這三個功能模塊進行著重分析。在對整個電路進行分析之后,采用國內(nèi)HHNECGE 0.35μm工藝對整個電路進行工藝移植。利用Hspice、Modelsim、ADMS模數(shù)混合仿真等仿真工具,分別對調(diào)制電路,解調(diào)電路以及整個電路進行各種測試以及模數(shù)混合仿真分析,通過仿真可以看出結(jié)果符合HART協(xié)議標準,各個功能模塊工作正常,功耗大約為260μA。最后進行版圖評估,面積大約為4000μm×4000μm,評估的面積只作為最終設(shè)計的面積參考。
[Abstract]:The HART protocol is the abbreviation of the addressable remote transmitter data channel protocol. In 1985, Rosement Company of the United States introduced a protocol protocol for two-way communication between intelligent instruments and control room devices. Hart protocol physical layer uses FSK-modulation and demodulation technology. A digital signal with an amplitude of 0.5 Ma is superimposed on the 4mA-20mA analog signal, The "1" and "0" of digital signals are replaced by 1200Hz and 2200Hz AC signals, respectively, so that analog communication and digital communication are simultaneously carried out and the .Hart protocol is a transitional product in the process of the transition from analog system to digital system. Therefore, in the current transition period, it has strong market competition ability and has been developed rapidly. This paper introduces a kind of HART protocol chip based on foreign process design, which is designed by reverse analysis. Combining with the standard of HART protocol. Firstly, by using Chip Logic net table extractor to recognize the device and digital logic gate of layout photo, Then the circuit diagram of each function module is arranged according to the instruction of the chip. When the digital circuit is arranged, the deep level analysis from gate level to RTL level is especially difficult. And it is time-consuming and laborious. In this paper, a method of deep level analysis of digital circuits is proposed, which greatly shortens the analysis time. Finally, the domestic technology is selected to transplant the circuit according to the theoretical knowledge and the instructions. And the functional modules are simulated and verified by relevant software. Some modules that do not meet the original design requirements will be redesigned. The whole HART protocol chip is divided into modulation circuit, demodulation circuit, and the whole HART protocol chip is divided into modulation circuit, demodulation circuit, and the whole HART protocol chip is divided into modulation circuit, demodulation circuit, and the whole HART protocol chip is divided into modulation circuit and demodulation circuit. Three parts of the common circuit. These three parts are the key parts of the whole circuit, so the three functional modules are analyzed emphatically. After the analysis of the whole circuit, The whole circuit is transplanted with HHNECGE 0.35 渭 m process in our country. The modulating circuit, demodulation circuit and the whole circuit are tested and analyzed respectively by using the HspiceMacksimsima ADMS mixed simulation tools, such as modulating circuit, demodulation circuit and the whole circuit. The simulation results show that the results conform to the standard of HART protocol, each functional module works normally, and the power consumption is about 260 渭 A. finally, the layout is evaluated, the area is about 4000 渭 m 脳 4000 渭 m, and the area evaluated is only used as the reference area of the final design.
【學(xué)位授予單位】：沈陽工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN915.05

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