本文關(guān)鍵詞： 電荷泵鎖相環(huán) 小數(shù)分頻器 正交環(huán)形振蕩器 Σ-Δ調(diào)制器　出處：《深圳大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：基于鎖相環(huán)的頻率合成器被廣泛應(yīng)用于國民生活和軍事領(lǐng)域中,如計(jì)算機(jī)、雷達(dá)、通訊、空間勘探、航天、航海等。此外,鎖相環(huán)還可以用于產(chǎn)生無線通信中的本地振蕩信號(hào);可以從接收機(jī)的調(diào)制信號(hào)中恢復(fù)基帶數(shù)據(jù);可以靈活作為調(diào)制器適用于不同的調(diào)制和解調(diào)電路。由于數(shù)�；旌想娐樊�(dāng)今發(fā)展趨勢勁頭迅猛,混合型鎖相環(huán)的結(jié)構(gòu)越來越多樣化,綜合性能也越來越強(qiáng)。傳統(tǒng)的整數(shù)型鎖相環(huán)輸出頻率的解析度較低,無法滿足一些高解析度的系統(tǒng)要求,而小數(shù)型鎖相環(huán)正好能夠在晶振頻率足夠高的情況下實(shí)現(xiàn)較高的輸出解析度。雖然全數(shù)字鎖相環(huán)的設(shè)計(jì)具有靈活性和可移植性,但是在對(duì)系統(tǒng)需求高的主流電路應(yīng)用里很多還是使用數(shù)模混合鎖相環(huán)。本文使用數(shù)模混合的電路設(shè)計(jì)流程,設(shè)計(jì)了一款寬帶小數(shù)N分頻的電荷泵鎖相環(huán)。本文主要工作以及創(chuàng)新點(diǎn)具體體現(xiàn)在于以下四點(diǎn):1)基于SP-MASH技術(shù)的Σ-Δ調(diào)制器。本文設(shè)計(jì)了一款輸入小數(shù)位寬為12bit,后級(jí)累加器位寬為20bit的SP-MASH小數(shù)調(diào)制器。該SP-MASH小數(shù)調(diào)制器同時(shí)綜合了MASH結(jié)構(gòu)和HK-MASH結(jié)構(gòu)的優(yōu)點(diǎn),既有HK-MASH結(jié)構(gòu)相媲美的輸出序列周期長度,又保證了如MASH的線性輸入,同時(shí)也避免從輸入引入噪聲,極大減少Σ-Δ調(diào)制器對(duì)鎖相環(huán)相位噪聲的影響。仿真結(jié)果表明本文所設(shè)計(jì)SP-MASH結(jié)構(gòu)Σ-Δ調(diào)制器具有優(yōu)秀的噪聲整形特性。在50MHz的時(shí)鐘下輸出底噪小于-200dB,輸出周期序列長度最大值為242。2)高電源噪聲抑制比的正交多路環(huán)形振蕩器(QVCO)。該QVCO的最大特點(diǎn)是頻率在一定范圍內(nèi)對(duì)電源變化不敏感,可以不使用LDO或者其他電源管理技術(shù)提高VCO的抗電源噪聲能力。通過仿真得到其歸一化電源靈敏度最小值為-46dB。VCO使用了壓控電阻的調(diào)諧手段,本文所設(shè)計(jì)的VCO的輸出頻率調(diào)諧范圍為440MHz-5.18GHz,輸出5GHz時(shí)的相位噪聲為-93dBc/Hz@1MHz。3)高速TSPC 4/5雙模預(yù)分頻器。該預(yù)分頻器采用偽2/3分頻器結(jié)構(gòu),減少了關(guān)鍵路徑上的延遲進(jìn)而極大提高了最大工作頻率,其可工作在4MHz~5.5GHz內(nèi)。在相同工藝下最高工作頻率比傳統(tǒng)結(jié)構(gòu)高40%。4)基于調(diào)節(jié)式共源共柵(Regulated Cascode,RGC)技術(shù)的雙電荷泵環(huán)路結(jié)構(gòu)。調(diào)節(jié)式共源共柵技術(shù)極大提高了電荷泵輸出動(dòng)態(tài)范圍,在0.2-1.6V控制電壓內(nèi)其電流失配小于0.6%。鎖相環(huán)環(huán)路中采用了雙電荷泵結(jié)構(gòu),與傳統(tǒng)單電荷泵結(jié)構(gòu)相比極大地減少了鎖定時(shí)間。本文采用SMIC 0.18umCMOS工藝設(shè)計(jì)了一款寬帶小數(shù)N分頻的電荷泵鎖相環(huán),其輸出頻率范圍為1.5GHz-4.5GHz,步進(jìn)約為12KHz。電路仿真表明CPPLL輸出頻率為4.5GHz時(shí),相位噪聲為-94.36dBc/Hz@1MHz,在1.8V電源電壓下消耗最大電流為25.8mA,PLL輸出鎖定時(shí)間低于8us。本次設(shè)計(jì)的鎖相環(huán)在同類型結(jié)構(gòu)PLL中輸出頻率范圍和鎖定時(shí)間都有一定的優(yōu)勢。
[Abstract]:The frequency synthesizer based on PLL is widely used in Yu Guomin's life and military fields, such as computer, radar, communication, space exploration, spaceflight, navigation and so on. The PLL can also be used to generate local oscillation signals in wireless communication. Baseband data can be recovered from the modulated signal of the receiver; It can be flexibly used as modulator for different modulation and demodulation circuits. Due to the rapid development trend of digital-analog hybrid circuits, the structure of hybrid PLL is becoming more and more diverse. The traditional integer PLL has lower resolution of output frequency and can not meet some system requirements of high resolution. The decimal PLL can achieve high output resolution at high enough crystal frequency, although the design of all-digital PLL is flexible and portable. However, in the mainstream circuit applications with high demand for the system, a lot of digital-analog hybrid phase-locked loops are used. In this paper, the digital-analog hybrid circuit design process is used. A charge pump phase-locked loop (CPPLL) with wide band fractional N frequency division is designed. The main work and innovation of this paper are as follows: 1). 危-螖 modulator based on SP-MASH technology. A 12bit width input decimal is designed in this paper. SP-MASH decimal modulator with 20 bit bit width of the latter accumulator. The SP-MASH decimal modulator combines the advantages of both the MASH structure and the HK-MASH structure. Not only the output sequence cycle length of HK-MASH structure is comparable, but also the linear input such as MASH is guaranteed, and the noise is avoided. The effect of 危-螖 modulator on phase noise of PLL is greatly reduced. The simulation results show that the 危-螖 modulator designed in this paper has excellent noise shaping characteristics. The output bottom noise is less than -200dB. Maximum output period sequence length 242.2) Quadrature multichannel ring oscillator with high power noise suppression ratio QVCO). The main characteristic of this QVCO is that the frequency is insensitive to the change of power supply in a certain range. LDO or other power management techniques can be used to improve the power noise resistance of VCO. The results of simulation show that the minimum sensitivity of normalized power supply is -46dB.VCO using the tuning of voltage-controlled resistor. Means. The output frequency tuning range of the designed VCO is 440 MHz to 5.18 GHz. The phase noise at 5GHz is -93dBc / Hz @ 1MHz 路3) high speed TSPC 4/5 dual-mode predivider with a pseudo-#number1# frequency divider structure. The delay on the critical path is reduced and the maximum working frequency is greatly increased. It can work in the range of 5. 5GHz. The maximum operating frequency is 40. 4 higher than that of the traditional structure in the same process. The double charge pump loop structure of RGC technology. The adjustable common-gate technology greatly improves the dynamic range of charge pump output. The current mismatch within 0.2-1.6V control voltage is less than 0.6. The dual charge pump structure is used in the PLL loop. Compared with the traditional single charge pump structure, the locking time is greatly reduced. In this paper, a charge pump phase-locked loop with wide band fractional N frequency division is designed using SMIC 0.18 m CMOS process. The output frequency ranges from 1.5 GHz to 4.5 GHz, and the step is about 12 KHz. The circuit simulation shows that the output frequency of CPPLL is 4.5 GHz. The phase noise is -94.36dBc / Hz @ 1MHz, and the maximum current consumption is 25.8mA at 1.8 V supply voltage. The output locking time of PLL is less than 8 us. the designed PLL has some advantages in the output frequency range and locking time in the same type of PLL.
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN911.8;TN761

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