本文關(guān)鍵詞：基于三值光學(xué)計(jì)算機(jī)的并行快速Fourier算法實(shí)現(xiàn)　出處：《中國科學(xué):信息科學(xué)》2017年07期 　論文類型：期刊論文

  更多相關(guān)文章： 三值光學(xué)計(jì)算機(jī) 快速Fourier變換 并行計(jì)算 MSD加法器 嵌入式設(shè)備

【摘要】：快速Fourier變換(FFT)是信號處理領(lǐng)域應(yīng)用十分廣泛的算法,在高速、實(shí)時(shí)的應(yīng)用環(huán)境中常用硬件并行實(shí)現(xiàn)的方法來加快FFT的運(yùn)算速度,但在一些特定領(lǐng)域如在空間受限、對能耗及散熱具有較高要求的航空航天設(shè)備中,傳統(tǒng)的電子方法將受到很大的局限,而三值光學(xué)計(jì)算機(jī)以其能耗低、數(shù)據(jù)位數(shù)眾多的優(yōu)點(diǎn)使得它可能具有廣泛的應(yīng)用前景.針對這種現(xiàn)狀,本文研究了采用三值光學(xué)計(jì)算機(jī)來實(shí)現(xiàn)快速Fourier變換的設(shè)計(jì)方案和方法.通過對傳統(tǒng)基2、基4和基8時(shí)域抽取快速Fourier變換運(yùn)算過程的分析,利用三值光學(xué)計(jì)算機(jī)數(shù)據(jù)位數(shù)眾多和數(shù)據(jù)位數(shù)易擴(kuò)展的特點(diǎn)設(shè)計(jì)了多個(gè)并行度更高的快速Fourier變換算法,給出了詳細(xì)的算法實(shí)現(xiàn)流程并進(jìn)行了各算法間的對比,分析了實(shí)現(xiàn)方案所需的時(shí)鐘周期和硬件資源,模擬驗(yàn)證了該實(shí)現(xiàn)方案的正確性.相比于傳統(tǒng)基于現(xiàn)場可編程門陣列的并行實(shí)現(xiàn)方法,這種在三值光學(xué)計(jì)算機(jī)上實(shí)現(xiàn)的快速Fourier變換運(yùn)算功耗更低、所需時(shí)鐘周期數(shù)更少,這為在嵌入式設(shè)備中高速低功耗地實(shí)現(xiàn)快速Fourier變換提供了新的解決思路.
[Abstract]:Fast Fourier transform (FFT) is a widely used algorithm in the field of signal processing. In high speed and real time application environment, the hardware parallel implementation method is commonly used to speed up the operation speed of FFT. However, in some special fields, such as limited space, high requirements for energy consumption and heat dissipation, the traditional electronic methods will be greatly limited, while the ternary optical computer with its low energy consumption. The advantages of a large number of data bits make it possible to have a wide range of application prospects. In this paper, the design scheme and method of fast Fourier transform using ternary optical computer are studied. The analysis of the fast Fourier transform operation in the time domain decimation of base 4 and base 8. Taking advantage of the large number of data bits in ternary optical computers and the easy expansion of data bits, several fast Fourier transform algorithms with higher parallelism are designed. The detailed implementation flow of the algorithm is given, and the comparison among the algorithms is carried out, and the clock cycle and hardware resources required for the implementation are analyzed. Compared with the traditional parallel implementation method based on the field programmable gate array, the fast Fourier transform implemented on the ternary optical computer has lower power consumption. The number of clock cycles required is even less, which provides a new solution for fast Fourier conversion in embedded devices with high speed and low power consumption.
【作者單位】： 上海大學(xué)計(jì)算機(jī)工程與科學(xué)學(xué)院;中國科學(xué)院上海高等研究院;毫米波遙感技術(shù)國家級重點(diǎn)實(shí)驗(yàn)室;
【基金】：國家自然科學(xué)基金(批準(zhǔn)號:61572305,61103054) 中國航天科工集團(tuán)二院“自主”創(chuàng)新項(xiàng)目資助
【分類號】：TN911.7
【正文快照】： 1引言快速Fourier變換(FFT:fast Fourier transformation)[1]作為在數(shù)字信號處理領(lǐng)域的重要工具,在雷達(dá)信號分析、圖像處理、語音分析等應(yīng)用中被廣泛使用.針對高速、實(shí)時(shí)的應(yīng)用場合,目前常見的FFT硬件加速器采用基于流水線的單路徑延時(shí)反饋結(jié)構(gòu)[2]或者各級內(nèi)蝶形變換并行處理

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