本文關(guān)鍵詞：基于FPGA的高速數(shù)據(jù)采集卡的設(shè)計　出處：《山東大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： FPGA SD卡 高速數(shù)據(jù)采集

【摘要】：在北斗導(dǎo)航系統(tǒng)中,基于軟件無線電思想設(shè)計的軟件導(dǎo)航接收機包括硬件前端、中頻信號處理、導(dǎo)航解算。經(jīng)大氣傳播的導(dǎo)航衛(wèi)星信號到達接收機天線,由射頻前端對它進行放大、下變頻、濾波、采樣、量化處理后,得到數(shù)字中頻信號。當(dāng)導(dǎo)航衛(wèi)星信號經(jīng)過下變頻、濾波之后,再對其進行采樣、量化,得到一個高速的數(shù)字信號,為了便于采集導(dǎo)航中頻信號以作為基帶處理芯片的輸入,需要一個高速的數(shù)據(jù)采集卡完成數(shù)據(jù)的采集工作。因此,一個高速的數(shù)字信號存儲模塊就是完成導(dǎo)航中頻信號采集必不可少的一部分。本文利用緩存、串并轉(zhuǎn)換實現(xiàn)數(shù)據(jù)降速,然后采用低速設(shè)備完成高速數(shù)據(jù)的存儲工作。整體分為兩個模塊,數(shù)據(jù)分流存儲模塊和數(shù)據(jù)整合模塊。數(shù)據(jù)分流存儲模塊是通過借助緩存實現(xiàn)數(shù)據(jù)的存儲;數(shù)據(jù)整合模塊是將在數(shù)據(jù)存儲時打亂的數(shù)據(jù)整合到一起。固態(tài)硬盤的成本比較高,所以論文選擇用SD卡作為數(shù)據(jù)存儲單元。SD卡作為一種基于半導(dǎo)體快閃存儲器的新一代存儲設(shè)備,被廣泛應(yīng)用于便攜式設(shè)備之中。但是由于SD卡的存儲速度達不到使用要求,因此本文設(shè)計了以下方案來完成數(shù)據(jù)的存儲工作。論文通過串并轉(zhuǎn)換的方式以完成利用低速設(shè)備存儲高速數(shù)據(jù)工作,具有非常好的便攜性。本論文通過借助緩存降低數(shù)據(jù)速度:首先利用乒乓操作對一組高速串行的數(shù)字信號進行串并轉(zhuǎn)換,實現(xiàn)降速功能。然后進行多路數(shù)據(jù)的存儲。本論文選用4bit-SD總線模式實現(xiàn)數(shù)據(jù)的存儲過程,即將降速后的數(shù)據(jù)存儲到多個SD卡中。在數(shù)據(jù)降速過程中,一路串行數(shù)據(jù)被分成了多路并行數(shù)據(jù),原來數(shù)據(jù)的排列方式被打亂,后期需要將數(shù)據(jù)恢復(fù)成原來的排列方式,將多路數(shù)據(jù)整合成最初一路串行數(shù)據(jù):依次從多個卡中讀取數(shù)據(jù),實現(xiàn)數(shù)據(jù)的并串轉(zhuǎn)換,最終得到一路串行的數(shù)據(jù),然后以較低的速度存儲到一個卡中,完成數(shù)據(jù)的存儲和整合過程。后期的并串轉(zhuǎn)換是在數(shù)據(jù)采集完成后,因而有充足的時間進行數(shù)據(jù)的多路合并,對合并后的數(shù)據(jù)速率要求也較低。本文的設(shè)計使用verilog HDL編寫了 RTL級代碼,選用Mentor Graphics公司的Modelsim10.0作為仿真工具,進行功能仿真。在硬件驗證階段,選用ALTERA公司的DE2開發(fā)板,其中FPGA芯片型號為Cyclone ii-EP2C35F672C6N。經(jīng)過硬件驗證,單卡的數(shù)據(jù)讀寫速率能達到49Mb/s,當(dāng)選用4張SD卡來完成數(shù)據(jù)的存儲時,存儲速率可達到200Mb/s,可以滿足數(shù)據(jù)存儲速度的要求。
[Abstract]:In the Beidou navigation system, the software navigation receiver based on the idea of software radio includes the hardware front end, if signal processing, navigation calculation. The navigation satellite signal propagates through the atmosphere to the receiver antenna. It is amplified, down-converted, filtered, sampled and quantized by RF front-end, and the digital intermediate frequency signal is obtained. When the navigation satellite signal is down-converted and filtered, it is then sampled and quantized. To obtain a high-speed digital signal, in order to collect navigation intermediate frequency signal as the input of baseband processing chip, a high-speed data acquisition card is needed to complete the data acquisition. A high-speed digital signal storage module is an essential part of the navigation if signal acquisition. This paper uses cache, series-parallel conversion to achieve data speed reduction. The whole system is divided into two modules, data streaming storage module and data integration module. Data streaming storage module realizes data storage by means of cache. The data consolidation module is the integration of data that is disrupted while storing data. The cost of solid state hard drives is high. Therefore, SD card is chosen as the data storage unit. SD card is used as a new generation storage device based on semiconductor flash memory. It is widely used in portable devices, but the storage speed of SD card can not meet the requirements. Therefore, this paper designs the following scheme to complete the data storage. The paper uses series-parallel conversion to achieve the use of low-speed devices to store high-speed data. This paper reduces the speed of data by means of cache. Firstly, we use ping-pong operation to transform a group of high-speed serial digital signals into parallel. In this paper, we choose 4bit-SD bus mode to realize the data storage procedure. The data will be stored in multiple SD cards. In the process of data deceleration, one serial data is divided into multiple parallel data, the original data arrangement is disrupted. In the later period, we need to restore the data to the original arrangement mode, and integrate the multi-channel data into the original serial data: read the data from multiple cards in turn, realize the serial data conversion, and finally get the serial data. Then stored in a card at a low speed to complete the process of data storage and integration. The later parallel string conversion is after the completion of data acquisition, so there is sufficient time for data multiplexing. The design of this paper uses verilog HDL to write RTL level code. The Modelsim10.0 of Mentor Graphics Company is chosen as the simulation tool, and the function simulation is carried out in the stage of hardware verification. The DE2 development board of ALTERA company is selected, in which the FPGA chip model is Cyclone ii-EP2C35F672C6N. it is verified by hardware. The data reading and writing rate of single card can reach 49MB / s. When 4 SD cards are used to store data, the storage rate can reach 200MB / s, which can meet the requirement of data storage speed.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN965.5

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